Join us at the 53rd Design Automation Conference DAC is always a time of jam-packed activity with multiple events that…
A few weeks ago I had the honor of presenting a paper related to my prior Verification Horizons blog posts…
Just over a decade ago, Mentor Graphics had initiated a technology forum in India called the ‘EDA Tech Forum’, this…
Having been deeply involved with Universal Verification Methodology (UVM) from its inception, and before that, with OVM from its secret-meetings-in-a-hidden-hotel-room…
Using SystemVerilog to model RTL behavior in a pinch or anytime A couple weeks ago, sitting here in California on…
Does anybody remember Daisy PLDMaster? Okay, Methuselah, you can put your hand down now. Some time back in the late…
We have talked about how one can go from ‘No to Know VIP’ in my 3 part series and how…
If you were wondering whether formal verification is becoming a cornerstone of mainstream verification flows, several events at the recent…
As I’m sure I’ve mentioned before, DVCon (in the US – I haven’t made it to any of the new,…
