To understand how techniques fit together as part of a comprehensive verification methodology, we’re mapping techniques as a function of…
SystemVerilog allows you to create modules and classes that are parameterized. This makes them more flexible, and able to work…
I think most project teams agree that there is a lot of benefit in adopting UVM in terms of improving…
Discussion around verification methodologies have been going on for a couple decades. It started back around 2000 with the emergence…
As always, the Mentor team was a substantial part of the program at this year’s DVCon US. Unfortunately, due to…
Or: What I forgot in class When I first learned UVM, there were many things that baffled me. What was…
A few months ago I had the honor of being invited to lecture a graduate-level course on functional verification. After…
In early February, I had the honor of keynoting the FPGA-forum held in the beautiful city of Trondheim, Norway. This…
Verification methodology has been a continuous discussion in our industry for a good 20 years now. I’ve dabbled in that…
