Portable Stimulus and VIP: Like a Hand in a Glove

One of my favorite things about DAC is the ability to share with so many of you some details of…

Circuit board with chip and binary data depicting interface Protocol Verification

Announcing Avery UCIe 2.0 Verification IP from Siemens EDA

Announcement: Siemens EDA are excited to announce availability of our Verification IP products for UCIe version 2.0, coincident with today’s…

Verification Challenges and Solutions for Multi-Die Systems (UCIe) 

Introduction Multi-die systems accelerate the scaling of system functionality, reduce risk, and facilitate the creation of new product variants. However,…

Accelerating Verification of Computational Storage Designs (NVMe)

Introduction Computational storage is revolutionizing data storage by embedding computational capabilities within storage devices, significantly boosting system efficiency by reducing…

Accelerate Closure of Reset Path and Reset Domain Crossing Issues in Digital Designs

In today’s large, complex designs, multiple asynchronous resets have become the norm. The increase in reset domains is driven by…

Join us at Accellera’s DAC Luncheon to discuss PSS

Portable Test & Stimulus Standard Takes Center Stage at Accellera’s DAC Luncheon.  The luncheon will be held on Tuesday, June…

Learn About the Security-critical CMA/SPDM, DOE, IDE, and TDISP elements of the PCIe protocol at the 2024 PCI SIG DevCon

The Peripheral Component Interconnect Express (PCIe®) protocol is incredibly feature rich; so much so that even experienced engineers can struggle…

Mark your calendar for the 2024 DAC-Chips to Systems Conference

Get ready and mark your calendars for DAC 61 – the Chips to Systems Conference you won’t want to miss!…

Simulation is Key in design verification process

The importance of simulation in the pursuit of absolute speed!

A casual conversation with an ex-insider of the high frequency trading sector reveals surprising details about simulation and their design-verification process