Rich Edelman
The Grapes Are Back! And Cake! And C Tests with UVM and Transactions For All! Easy.

The Grapes Are Back! And Cake! And C Tests with UVM and Transactions For All! Easy.

September 8, 2025
The grapes have returned – this weekend was “harvest” time. Jelly everywhere. A lot like this year here at Siemens....
By Rich Edelman
< 1 MIN READ
Got Coverage?

Got Coverage?

February 14, 2025
Welcome to 2025. What happened?! “Coverage” in August in Yosemite backpacking has a different meaning. In August? Snow? Lots of...
By Rich Edelman
< 1 MIN READ
UVM Objections at DVCON US 2024 – and Grape Jelly

UVM Objections at DVCON US 2024 – and Grape Jelly

February 22, 2024
Boiling Grape Jelly Stay with me – trust me. There’s a tie in to UVM Objections and DVCON US 2024....
By Rich Edelman
< 1 MIN READ
Bent Tools and other Horrors From the Garden and UVM Debug – or Are You Still Debugging with $display?

Bent Tools and other Horrors From the Garden and UVM Debug – or Are You Still Debugging with $display?

May 25, 2023
I can’t take credit for the great flowers in the garden. It’s the tremendous rain we’ve had in California this...
By Rich Edelman
< 1 MIN READ
To UVM Config or Not at DVCON US – Can chatGPT do it better?

To UVM Config or Not at DVCON US – Can chatGPT do it better?

February 14, 2023
It’s all about speed and productivity for Verification Engineers and Designers. And of course, the UVM is the ticket, and...
By Rich Edelman
< 1 MIN READ
Register Testing the “Easy Way” at DVCON Europe

Register Testing the “Easy Way” at DVCON Europe

November 15, 2022
DVCON Europe is coming to Munich, December 6-7, 2022. Hope to see you there! I’ll be presenting a paper on...
By Rich Edelman
< 1 MIN READ
UVM Testbench Debug – A Day At The Beach – Right?

UVM Testbench Debug – A Day At The Beach – Right?

October 4, 2022
Some people think UVM Testbench Debug is a drag. But really, it depends. I think it’s a day at the...
By Rich Edelman
< 1 MIN READ
Finding Data

Finding Data

July 28, 2022
Finding Data Another weekend of weeding. Dark Star – Ceanothus – A California Lilac in the picture. (Not a weed)....
By Rich Edelman
< 1 MIN READ
Verilog & VHDL Debug & Weeding

Verilog & VHDL Debug & Weeding

May 18, 2022
A short exploration through using better debugging tools for better productivity.
By Rich Edelman
< 1 MIN READ
A UVM Scoreboard: Does it really have to be that hard?

A UVM Scoreboard: Does it really have to be that hard?

November 16, 2021
UVM Scoreboards don’t have to be hard But I’m getting ahead of myself. This week I gave up on my...
By Rich Edelman
< 1 MIN READ
Why Is My Coverage The Way It Is?

Why Is My Coverage The Way It Is?

September 2, 2021
Coverage is as Coverage does Writing coverage is an art. At least it is a skill which takes imagination, practice...
By Rich Edelman
< 1 MIN READ
The UVM : Is it Safe?

The UVM : Is it Safe?

October 31, 2019
Is It Safe? It depends. What is the context? Economy? Geo-political situation? Teenage drivers? UVM? I don’t know. Do you...
By Rich Edelman
< 1 MIN READ
Straight-up Smash-mouth Debug

Straight-up Smash-mouth Debug

April 30, 2019
I’m having a bad day. Lots of work. Lots of moving parts. We’ve all been there. Nothing new. >> Too...
By Rich Edelman
< 1 MIN READ
So You Want a Different UVM Report Server. Doesn’t Everyone? Where To Start…

So You Want a Different UVM Report Server. Doesn’t Everyone? Where To Start…

February 15, 2019
So. You want a different report server. Maybe something fancier. Maybe something simpler. Maybe something with special formatting. How to...
By Rich Edelman
< 1 MIN READ
Debugging Complex UVM Testbenches

Debugging Complex UVM Testbenches

January 11, 2018
Modern complex chips necessarily have modern complex testbenches. The testbenches of old – wiggling one pin at a time and...
By Rich Edelman
< 1 MIN READ
Holiday UVM Register Indigestion

Holiday UVM Register Indigestion

January 4, 2017
Happy Holidays! Hopefully, wherever you are you are enjoying some time off. At our house, we’re planning a large dinner,...
By Rich Edelman
< 1 MIN READ
Debugging My UVM Factory and UVM Config

Debugging My UVM Factory and UVM Config

October 7, 2016
UVM and Better Debug – The UVM Factory and Config conspire against me   Sitting in my chair pulling out...
By Rich Edelman
< 1 MIN READ
Still waiting… It’s Friday afternoon, and I don’t have my RTL

Still waiting… It’s Friday afternoon, and I don’t have my RTL

April 20, 2016
Using SystemVerilog to model RTL behavior in a pinch or anytime A couple weeks ago, sitting here in California on...
By Rich Edelman
< 1 MIN READ
What’s Going On With My SystemVerilog Queue?

What’s Going On With My SystemVerilog Queue?

January 29, 2016
I want my MTV! And while I’m at it, I’m also curious about what’s going on with my SystemVerilog queues....
By Rich Edelman
< 1 MIN READ
UVM Debug. A contest using class based testbench debug…

UVM Debug. A contest using class based testbench debug…

May 21, 2015
Still having fun doing UVM and Class based debug? Maybe a debug contest will help. I had a contest with...
By Rich Edelman
< 1 MIN READ
SystemVerilog Testbench Debug – Are we having fun yet?

SystemVerilog Testbench Debug – Are we having fun yet?

November 24, 2014
SystemVerilog Testbench Debug – Are we having fun yet? Fun Debug should be fun. Watching waveforms march by, seeing ERRORS...
By Rich Edelman
< 1 MIN READ