Interchange format standard in hierarchical CDC and RDC analysis

For large designs with numerous asynchronous clocks and resets, there is a growing need to do clock domain crossing (CDC) and reset domain crossing (RDC) analysis in a hierarchical way. This allows parallelization of sub-block and noiseless analysis and helps reduce SoC runtime and speed closure of CDC and RDC issues at the SoC level. Conversely, it poses challenges for design houses using third-party IP in ensuring the compatibility of their hierarchical data models (HDM) in the case of multiple EDA tools usage.