By Rick Fisette, Mentor Graphics Remove ATPG from the critical path to tapeout with hierarchical DFT plus test pattern retargeting…
By Rahul Singhal, Mentor Graphics Near-zero defect testing for safety-critical ICs means also testing the DFT logic.
By Ron Press, Mentor Graphics DFT with less risk to your design flow? Here’s how.
By Steve Pateras, Mentor Graphics Ensure quality and reliability in automotive ICs with the newest technologies in silicon test.
By Steve Pateras, Mentor Graphics Memory BIST is evolving to meet the demands of automotive ICs.
By Beth Martin with Steve Pateras, Mentor Graphics Mentor’s novel EDT test point technology dramatically reduces ATPG pattern volume
By Ron Press Inserting test compression logic just got a lot easier.
By Ron Press, Mentor Graphics Mentor’s EDT test points slash pattern count, test time and cost. But how about at-speed…
By Ron Press, Mentor Graphics Reuse block test patterns at the top level to control test time and cost with…
