Tessent’s ITC 2020 wrap-up

The International Test Conference carried on this year as a virtual event. It’s a difficult format to make work, but…

DFT and the competitive edge

Advanced DFT is your competitive edge Every new SoC project starts with grand hopes of glory. This one will be…

Tessent Wraps Up Summer Webinar Series

The summer of 2020 featured several new webinars from the Tessent Test Solutions group at Mentor, a Siemens business. These…

Video: ITC India 2020 keynote—Test community can take on silicon lifecycle challenges

The role of test is expanding from its traditional role into one that includes managing the entire silicon lifecycle. To…

Best practice in scan pattern ordering for test and diagnosis

Best practice in scan pattern ordering for test and diagnosis

By Jay Jahangiri and Wu Yang, Mentor Graphics By creating and applying scan patterns in the right order, you can…

What DFT history teaches us

What DFT history teaches us

By Stephen Pateras, Mentor Graphics Two DFT-related rules for success are as true today as they were 30 years ago

Hierarchical DFT: How to Do More, More Quickly, with Fewer Resources

Hierarchical DFT: How to Do More, More Quickly, with Fewer Resources

By Rick Fisette, Mentor Graphics Remove ATPG from the critical path to tapeout with hierarchical DFT plus test pattern retargeting…

Ensure defect-free automotive ICs with the Hybrid TK/LBIST solution that also finds faults in the DFT logic

Ensure defect-free automotive ICs with the Hybrid TK/LBIST solution that also finds faults in the DFT logic

By Rahul Singhal, Mentor Graphics Near-zero defect testing for safety-critical ICs means also testing the DFT logic.

Take scan test out of the critical path

Take scan test out of the critical path

By Ron Press, Mentor Graphics DFT with less risk to your design flow? Here’s how.