Slash test costs and reduce implementation effort for complex next-generation SoCs.
IC engineering teams have seen a dramatic rise in the time and cost required to test today’s large and complex IC designs. The challenges span from DFT implementation time and effort to time spent on manufacturing test.
In the latest salvo in the battle to control DFT and test time, effort, and cost, the Tessent team developed a revolutionary new technology in the flagship Tessent TestKompress. It’s called Streaming Scan Network (SSN), and it includes embedded infrastructure and automation that decouples core-level DFT requirements from the chip-level test delivery resources. This enables a no-compromise, bottom-up DFT flow that can dramatically simplify DFT planning and implementation, while reducing test time up to 4X. With full support for tiled designs and optimization for identical cores, it is ideal for increasingly large emerging compute architectures.
SSN is a bus-based scan data distribution architecture that enables simultaneous testing of any number of cores. It helps shorten test time by enabling high-speed data distribution, efficiently handling imbalances between cores, and supporting testing of any number of identical cores with a constant cost. It also provides a plug-and-play interface in each core that simplifies scan timing closure and is well-suited for abutted tiles.
The solution consists of a series of host nodes in each design block that are networked together. Each host distributes data between the network and the test structures in the block. The software automates the implementation, pattern generation, and failure reverse mapping processes. DFT engineers can fully optimize DFT test resources for each block without concern for impacts to the rest of the design. This helps to dramatically reduce the implementation effort. Along with optimized handling of identical cores, elimination of waste in the test data, and time multiplexing, this solution enables substantial reductions in test data time and volume.
The Tessent Streaming Scan Network capability in the Tessent TestKompress product is a result of more than 10 years of research and development in advanced hierarchical DFT implementation and test data bandwidth management. Mentor developed the technology in collaboration with multiple leading semiconductor manufacturers. SSN is fully compatible with all other Tessent DFT products and can be combined with Tessent Diagnosis cell-aware and layout-aware diagnosis for a complete end-to-end defect detection and diagnosis solution.
SSN had its debut at the 2020 International Test Conference and was represented in the technical sessions with a paper with Intel, “Streaming Scan Network (SSN): An Efficient Packetized Data Network for Testing of Complex SoCs.” The results of Intel’s experiments with SSN show significant value compared to their current technology (hier mux and their internal data delivery method, STF). Here’s what they saw with SSN:
- Reduced the test data volume by 36% and 43% (mux and STF)
- Reduced test cycles by 16% and 43%
- 10x – 20x faster with SSN compared to STF
SSN eliminates the tradeoffs between either an effective, streamlined implementation flow, or minimized test cost. SSN is a no-compromise approach to DFT leveraging packetized delivery of scan test data. It was developed over three years of partnerships and validated in silicon with 6 tapeouts in 2020.