Slash test costs and reduce implementation effort for complex next-generation SoCs. IC engineering teams have seen a dramatic rise in…
The International Test Conference carried on this year as a virtual event. It’s a difficult format to make work, but…
Advanced DFT is your competitive edge Every new SoC project starts with grand hopes of glory. This one will be…
The summer of 2020 featured several new webinars from the Tessent Test Solutions group at Mentor, a Siemens business. These…
The role of test is expanding from its traditional role into one that includes managing the entire silicon lifecycle. To…
By Jay Jahangiri and Wu Yang, Mentor Graphics By creating and applying scan patterns in the right order, you can…
By Stephen Pateras, Mentor Graphics Two DFT-related rules for success are as true today as they were 30 years ago
By Rick Fisette, Mentor Graphics Remove ATPG from the critical path to tapeout with hierarchical DFT plus test pattern retargeting…
By Rahul Singhal, Mentor Graphics Near-zero defect testing for safety-critical ICs means also testing the DFT logic.
