Image of a 3D IC with text that says TSMC 2024 NA OIP Ecosystem Forum

Join us at the TSMC 2024 NA OIP Ecosystem Forum

The TSMC 2024 North America OIP (Open Innovation Platform®) Ecosystem Forum is just around the corner, and Siemens EDA is…

User2User 2024: Chiplets for future automotive application: Fraunhofer

User2User 2024: Chiplets for future automotive application: Fraunhofer

Andy Heinig, Head of Department Efficient Electronics at Fraunhofer, explains why automotive is especially a good market and enabler for chiplets and presents different use cases for chiplets that are on the horizon.

A deep dive into HDAP LVS/LVL verification

EDA companies are developing tools and workflows to support HDAP (High-density advanced packaging) LVS/LVL verification. Though the data for achieving “signoff-level” confidence is a work in progress, EDA companies are providing tools that can adapt to different levels of data availability and enable HDAP designers to execute HDAP LVS/LVL flows that are both productive and beneficial.

Siemens 3D IC heterogeneous semiconductor packaging workflows catapult design teams into the future of IC design today.

Workflows for tackling heterogeneous integration of chiplets for 2.5D/3D semiconductor packaging

Workflows for tackling heterogeneous integration of chiplets for 2.5D/3D semiconductor packaging.

Impacts of 3D IC on the future

3D IC technology development started many years ago well before the slowing down of Moore’s law benefits became a topic…

What's new in Xpedition IC Packaging

What’s new in Xpedition IC Packaging VX.2.14

The new VX.2.14 release of Xpedition IC Packaging includes improvements and enhancements to both Xpedition Substrate Integrator and Xpedition Package…

system technology co-optimization

Shifting left with system technology co-optimization for IC packaging

We have witnessed and learned about the industry’s significant shift in semiconductors. The traditional approach of transistor scaling, once universally…

Illustration of 3D IC design workflows

Why co-design-driven semiconductor package planning and prototyping is critical for design success

The connectivity management complexity of package assemblies where multiple chiplets/ASICs and memory are heterogeneously integrated, introduces a great deal of…

Revolutionizing semiconductors with 3D IC and chiplet technology

Each Industrial Revolution resulted in advancements that propelled humans forward into a seemingly different world. The first in 1784 was…