Co-packaged optics chip

Five Key Trends of Co-Packaged Optics (CPO) in 2026

For years, data-center performance scaled by following a familiar playbook: faster GPUs, higher SerDes rates, and increasingly aggressive board designs….

Six IC packaging trends

Six Key Trends Redefining 3D IC Packaging in the AI Era

Some say we are officially in the Post-Moore’s Law world.  Moore himself closed his seminal paper by mentioning the “day…

From 2.5D to true 3D IC: What’s driving the next wave of integration.​

With 3D IC integration blurring the lines between chip and package, is your team’s mindset truly system-centric, or are traditional…

10 steps for successful heterogeneous chiplet integration

Unlock advanced chiplet design success: Discover the Siemens EDA Heterogeneous Integration eBook series

The future of semiconductor innovation is rapidly shifting from monolithic chips to advanced, multi-chiplet architectures. As devices demand greater power,…

Why every 3D IC needs a test vehicle before it hits production​

Would you risk millions of dollars on a semiconductor design without knowing if it can be manufactured? Discover why test…

Breaking down 50 million pins: A smarter way to design 3D IC packages​

As 3D IC complexity skyrockets, are we truly evolving our design methodologies at the same pace, or are we unknowingly…

Navigating signal integrity and power integrity (SI/PI) in 3D IC design​

Q: Is dedicated SI/PI analysis still necessary in 3D IC design? A: With the rapid advancements in chip design automation…

How to Design Smarter: System-level multiphysics in 3D integration​

What happens when a perfectly functioning chip fails to perform in a 3D IC package? As semiconductor designs stack multiple…

​Why 3D ICs need a mindset shift and how to make it happen

What if the most revolutionary advances in semiconductor design aren’t about making things smaller, but about fundamentally reimagining how we…