John McMillan (00:03.499)
We are witnessing a fundamental shift in semiconductor design. The International Technology Roadmap for semiconductors calls 3D IC technology not just an option, but a necessity for future electronic systems. Today, we’ll continue to explore why this technology is revolutionizing our industry. With that, welcome to the Siemens 3D IC podcast series, where we dive into the exciting world of semiconductor chiplet integration and advanced technology platforms using 2.5 and 3D techniques.
Brought to you by the Siemens Thought Leadership Team, I’m your host, John McMillan. In this podcast series, I talk with industry leaders and subject matter experts to discuss the latest 3D IC chiplet ecosystems, industry trends, and roadmaps. In today’s podcast, we’re going to be talking about hierarchical device planning of chiplets and interposers. And I’m excited to welcome my guest, Per Viklund, Director of IC packaging and RF product lines at Siemens EDA. Welcome, Per.
And before we dive into today’s discussion, please tell our listeners about yourself and your current role.
Per Viklund (01:05.542)
Hi John, thanks for having me. So as you mentioned, I’m in Siemens Digital Industries and I’m working in product strategy technology for IC packaging and RF microwave. And I’m actually on my 39th year doing that and being able to grow with how the technology has changed and evolved over that immense long time when we’re talking about electronics. Really exciting.
and I hope to celebrate my 40th year next year when we talk.
John McMillan (01:38.155)
Wow, that’s incredible. Really impressive. So we see big changes in IC packaging that I’m sure has a big impact to the whole ecosystem. It’d be interesting to get your view on this impact and what we can expect in the future.
Per Viklund (01:53.23)
Sure, you’re clearly thinking about chiplets and complexity scaling that’s really accelerating faster than ever. We have, for example, chiplets that are driven by the cost of making very large system on chips, where chiplets enable small, convenient building blocks that communicates with standard interfaces. On one side, and on the other side, we see how the complexity of packages are exploding. We saw package pin counts going from
maybe 100,000 or fewer pins in a package to 50 million pins or so these days. And we expect this to grow maybe 10X in the next few years. There is a huge impact to every corner of the ecosystem. Interface standards where we now have UCI Express, for example, BOW, AIS and so on, but also design methodology and tools that helps you with this and the whole interaction with the substrate fabricators and OSATs.
John McMillan (02:31.798)
Wow.
John McMillan (02:52.809)
You mentioned complexity several times in that. How do you manage that level of complexity?
Per Viklund (02:59.692)
Yeah, so this is clearly much more than any human can possibly oversee. So it would be impossible without a solution that reduces this complexity to the designer into something that is manageable by a person. So the solution is to work with abstraction levels. And key to this is the hierarchical device planning that you mentioned, which is really a methodology and a technology to break down the complexity into manageable portions.
John McMillan (03:31.969)
So let’s dig into that hierarchical device plane a little bit. What is it and how does it help manage all this complexity?
Per Viklund (03:40.014)
Let me try a short description. So, chiplets have many signals, interface IOs, power and ground, and you need to design a viable bump pattern for your chiplets and for your interposers and so on. And it’s a challenge to do this if you have maybe 100,000 pins that we had for some years ago. But it was doable, but errors happened.
For a million pins or 50 million pins, that’s absolutely not doable. It’s just out of the question. So this is where the hierarchical device planning comes in. So you hierarchically defined parameterized regions of component pins. And the designer works with these regions and can plan and design and analyze and optimize the design. But not really going into the details of every single pin with its connectivity until you actually need it.
we can then automatically synthesize all the pins according to all the parameters that we set on these pin regions. And as every package designer knows, you do get a lot of design changes during your design flow. But now instead of implementing every single change one by one, we can just modify the parameters and update a circuit automatically. It will save us days or even weeks sometimes. So that’s the key point of that.
John McMillan (05:02.569)
Great. So how was this done before within teams and what was that work process like and why can’t the traditional flow continue?
Per Viklund (05:15.82)
Yeah, the traditional tool for packaging of lower complexity and today we see it sometimes even for reasonably high complexity is really spreadsheets, Excel spreadsheets. It’s one of the most commonly used tools. And it may work fine for small designs, but now you have multiple chiplets with their interfaces. You have interposers or silicon bridges. And some of these pieces are being designed as you design the package, so they’re in flux.
and some may even be co-designed with the package. And you have to keep everything in sync and manage so much more data and keep it in sync. It’s not really viable by manual methods. We need solutions that manages the entire package assembly as a unit. So you can track connectivity through the entire package assembly and also provide some full package assembly verification in 3D. All these packages are…
some form of 3D packaging. So you need to validate that and verify it. You have to remember that now that the package is really multiple designs stacked together, we have the interposers and the chiplets and the silicon bridges and so on, the risk of failure would just be too large with traditional methods. So that’s why you need to go into a more synchronized design methodology.
John McMillan (06:37.697)
Gotcha, a lot of risk, apparently. How do designers manage those risks and what are the long-term consequences?
Per Viklund (06:46.638)
Starting with the consequences, right? If you are taping out a package assembly that has errors in it, there has been cases in history where that has had really astronomical consequences. It has brought down whole companies. That’s how massive the costs are when a big package is failing. The long-term consequence, assuming you survive and learn from your mistake, is that you never do that mistake again, right?
The way IC packaging is developing means that you must have the proper methodology and the proper tools for the job. So there are no ways around it.
John McMillan (07:24.825)
So when designers look for new adequate tools, what should those tools be able to do?
Per Viklund (07:33.614)
If we put it simply, they basically need to offer solutions to the designers challenges. First they need to isolate the designer from being stretched too thin, which is really what happens if you don’t have tools that can help you with the complexity. But they need to help the user to work at the practical abstraction level, one that makes the design manageable. You don’t just see 50 million pins.
that really doesn’t give you as a designer any clue how to do the design in an optimal way. And then they need to provide access to multi-domain analysis. And when I say so, mean, for example, signal integrity analysis, power integrity analysis, thermal analysis, thermal stress and work and so on. And to do that very, very early, long before you have done the package layout, for example, to help you drive
early design decisions to take the right path when you have choices. Because if you find major issues post layout, then it’s going to be extremely costly to go back. Many times it’s complete redesign of the package and you generally don’t have the time. So you want analysis very early. So that has to be there. So this is really why we at DAC this year are revealing our new Innovator 3D IC portfolio solution where we
cover the designer from this early planning and optimization through analysis and to package layout and also include work in progress data management because there is so much data going into a package today that you have to make sure you have the right versions of all the files that go in. If someone changed a Verilog file and you forgot to import it, you are building a package that’s incorrect. So that needs to be tracked and found automatically.
there’s too many areas where things can go wrong. This is not managed, right? So we put all this in the same Innovator 3D IC portfolio under the same AI infused user experience. So it should be quick and easy to pick up and use.
John McMillan (09:40.819)
great. This has been really informative. Any final comments before we wrap up this episode?
Per Viklund (09:49.208)
Well, as always, it’s always very nice to be here with you, John. I hope we can do it again sometime. I think the message I would kind of give to everyone in package design is that there are solutions out there. If they go out and look for it. Most designers have the feeling that what they’re doing is different from everybody else. And in some cases, that’s probably true. But in most cases…
they are all doing pretty much the same thing and are all inventing solutions to the same thing. So if you think about that for a while, it’s easier to find solutions. They are out there.
John McMillan (10:29.313)
Awesome. Great. Thanks, Per. Thanks for joining me today and sharing your knowledge and insights about the necessity and importance of hierarchical device planning of chiplets and interposers. Very informative session. That’s it for today’s episode of the 3D IC podcast. To all of our listeners and viewers, thanks for joining us today and be sure to check out the show notes to learn more about today’s topic. Also be sure to follow this podcast on YouTube or your favorite streaming service so you don’t miss the next episode of the 3D IC podcast.
Per Viklund (10:32.472)
Thank you.
