How to Design Smarter: System-level multiphysics in 3D integration​

Hello and welcome to the Siemens 3D IC podcast series, where we dive into the exciting world of semiconductor, chiplet integration and advanced technology platforms using two and a half and 3D techniques brought to you by the Siemens Thought Leadership Team. I’m your host, John McMillan. In this podcast series, I talk with industry leaders and subject matter experts to discuss the latest on 3D IC, chiplet ecosystems, industry trends and roadmaps. In today’s podcast, we’re going to talk about utilizing early predictive multi-physics analysis. And I’m excited how two great guests on the episode.

Firstly, returning guest, John Ferguson, Senior Director of Product Management for Calibre 3D IC Solutions at Siemens EDA. And joining the podcast for the first time is Tarek Ramadhan, Application Engineering Manager for 3D IC Technical Solutions here at Siemens EDA. Welcome back, John, and welcome Tarik. And before we dive into today’s discussion, please tell our listeners a little about yourself and your current roles. John, why you start us out?

Sure, I’ve been with Siemens slash Mentor Graphics for more than 25 years now. Spent a lot of my time in DRC, but also have traditionally been on kind of the forefront of newer technology. So I got involved with 3DIC maybe 15 years ago, and it’s had its fits and starts, but now we’re clearly in a domain where it’s becoming ubiquitous. So.

That’s kind of my role here. My role is to lead our 3DIC products from the Calibre side. At Siemens, we have lots of organizations that also delve into 3DIC. And so we’ll maybe hit on some of what they do as well, depending on where this goes.

I’m Tarek. I have been with Siemens ADA Mentor Graphics for 12 years. I used to work on the Calibre 3D IC organization, but three years ago I moved more to the technical sales side. We are a team of 16 3D IC specialists who work with customers to deploy and position our Siemens 3D IC solution.

And we have special focus on the system level integration and verification of 3D ICs.

Thanks guys, glad to have you here. So as we shift to 3D IC, how is the design process changing in comparison to two and two and a half D?

I think there’s a lot of differences. In the 2D space, we’ve kind of had it down fairly well for many years, right? Building an SoC, we know how to do it. We have very clear and strong PDKs and the software that goes along with those PDKs to make sure that every step along the way, you’re making significant progress towards having something that you know one is going to yield sufficiently and is going to actually perform the functions that you want within given certain specifications.

For 3DIC, that’s a lot more difficult. You’re bringing in heterogeneous chips, different processes, so you can’t have a single PDK. Makes it very challenging. You have issues of new materials, right, all the packaging materials that come in and different forms of interconnections through the package materials to the different chiplets. Those throw some new wrenches at us. And we’ll talk about some of that, but for me, the biggest concern is this multi-physics issue, which really, ultimately, it comes down to heating, right? We’re trying to power up multiple chips. When you’re powering up the chips, have to, we’re pushing electrons through wires. The wires are gonna get hot, and that’s gonna change

the behavior of a lot of things. One, it changes the behavior of the transistors themselves, but also it then heats up surrounding materials. Materials will have different levels of coefficients of mechanical stresses that get changed because of that. These all play in on each other. So this kind of combination of power to heat to stress has to be captured. If you have traditional known good die or known good chiplets. Maybe they’re small, in some cases not so small. When you’re testing those on a test bench, they might run just fine the way you expect them to run.

But when you put them in the context of a package, now this is when things start to change, right? You have heat that you didn’t have before, you have stresses that you didn’t have before. It’s possible the electrical behavior no longer meets what you had designed it to do in those conditions. So you have to be very, very careful.

Gotcha. what is multi-physics and how does it impact 3D IC design?

I don’t really like the term multi-physics because all physics is multi-physics, right? You can’t avoid the different forces that exist on our planet, right? So it doesn’t really matter much in that sense. But in this particular case, what we’re talking about, what multi-physics means from a 3DIC perspective, it means exactly those things. When you had an SOC and everything was all on one chip with one process behind it, you had…

a lot of capabilities to minimize certain impacts or some cases to more easily capture impacts like stresses for example or heating issues. You can largely make decisions to essentially set your design rules so that things aren’t so close that they’re going to be impacted.

Now we’re putting chips on top of chips. You have TSVs, have bumps, you have package materials. These things all behave very differently than a piece of silicon would. So now you can’t get away with minimizing or avoiding checking these things at all. You have to really look at them.

The bigger problem comes in, we know how to do heat, for example. We’ve had ways of checking heat and its impacts for a long time. Historically, that’s at the package level and it doesn’t really consider what’s inside of the chip which means you lose some accuracy, but there’s a different issue, right? You could put all these chips together, place them all nicely, and then you could go do a sign-off analysis to check the power, the heat, the stresses, to see are you going to behave electrically the way you expected.

But the problem is if you find out that you do have a problem, you don’t have any more time, right? You’re at the end of your design cycle. So you have to do these things early. You have to get in at the very beginning from floor planning stages all the way through. As your chips become more mature, maybe you have just the left or maybe you have just the deaf or you have maybe you have a chip, but not the fill in yet. Every time you are making improvements, you’ve got to redo these iterations to make sure that you haven’t done something that’s going to throw you off.

Sounds like it could have potential for a lot of problems. How is that impacting design teams?

I think the main challenge we see every day is different and more more teams are working on the same 3DIC product or design. So you have die teams, interposer teams, packaging teams, and even more recently we started to see ESD teams and RTL definition teams taking an interest and working on this.

The challenge with this is twofold. One is the difference in design methodologies. So that results into differences in data formats being used and exchanged between different teams. The other side is the difference in perspective. So you can see the same physical component being looked at differently by different teams.

So eventually it will be one component in the assembly, but it can be looked at differently from an orientation perspective or things like different net naming and definition methodologies.

This challenge really results into the need to have a system level owner or even a system level EDA platform that can help the design teams aggregate the data and unify the methodologies because the difference in methodologies is where the mistakes can happen. And you can imagine the amount of stress put into the system level owner in that case because he has to deal with the different teams with the different methodologies.

And there is a lot of moving parts and moving targets here. So this is where we try as an ED vendor to help this kind of role, like the system level owner, to aggregate data and make sure no mistakes happen across the way.

Something a little bit interesting in that aspect. Traditionally, and again, if I compare against the traditional SoC, particularly where you’re doing digital routing approaches, the approach there, you’re starting essentially with Verilog, right? And what’s not always clear is that when you’re at the Verilog level, you’ve already made a lot of the decisions that are gonna dictate how that chip behaves.

As we go into 3DIC, For digital design, that hasn’t been so bad, right? In traditional SOC style, that hasn’t been so bad. As we go into 3DIC, now you really, think, one, it’s new. And so you have some concerns, right? Are you getting all you can out of this? There’s this interest now in companies saying, I could do something that essentially says, OK, I’ve got a bunch of chips. Now I’m just kind of routing them together just in a 3D sense.

The problem is you don’t know what you’re giving up because you’ve started at that level. And so there’s a lot of companies saying, I want to have something that gives me more first level physics principle feedback so that I can make determinations. I know how this is going to be used in the wild. I want to make it as optimal as possible. It’s a very Interesting approach here that’s coming out.

But on a higher level, how is it impacting collaboration within companies or between teams or even between companies?

When I think of between companies, the first thing I think about is this idea of having off the shelf chips that can go into various packages. It’s pretty interesting, it’s pretty exciting, but again, it has its concerns, right? As I was saying, you can have a chip that runs perfectly by itself, but when you put it into that package, it could behave differently. If you’re not careful, you could be out of spec.

That, I think, is starting to be part of not just the only reason, but part of the reasons why you see a lot of effort for new standards, for example. The different parties involved need to have a common language, if you will, on how do we just describe these things, how do we pass it from one tool into another to ensure that we’re not going to have these kinds of issues appear. To me, that’s pretty interesting.

That also kind of lends itself to a cross EDA or cross design platforms, right? Where we have setups like the TSMC 3D blocks, for example, right? Where we can define where all the things are supposed to be placed upfront. So there’s no ambiguity that can go in and out of different tools. We can communicate with each other. Then you’re not dependent on a single vendor or you can choose the tools in the supply chain that make the most sense for you and your needs.

Just to add to what John mentioned, I think the same challenge we talked about regarding the different teams in the same company, you can scale the same challenge outside the company.

So you have the Fabless Design House, you have the Foundry, you have the OSAT or the Packaging House. And traditionally, those parties had different methodologies on how they do things. So as part of our effort as an EDA vendor who’s part of the ecosystem, we try to work with all these different entities and provide the needed tools and methodologies to make it easier to exchange data.

Like John mentioned, we have great efforts from TSMC, for example, to provide the 3D block standards, which should be able to facilitate this process.

Is any of this including what I’ve heard called 3D PDKs, 3D IC PDKs? Is that part of that?

Yes, exactly. So the way 3D blocks, there are a few other formats that compete a bit with 3D blocks. I know 3D blocks a little better. The way 3D blocks has been put together is one, a way to communicate, as I said, you know, here’s what’s in your package, the way you’ve designed it and where they all land three dimensionally.

But they also have focused on particular design flows. How do I get from point A to point B in my designing? And that’s, think, been a really nice piece of it.

I think another thing, when I think about collaborations, if you will, between companies, another thing that becomes important is this idea of a digital twin. This chip, you’ve got a chip that goes in a package, you’ve got a package that goes onto a board, you’ve got a board that maybe goes into an automobile or onto a jet or in a computer or in a server farm, right?

Making sure that we have a path that goes from all the way from that chip level, from the transistor level, all the way through to the whole system so that you’re getting the utmost accuracy when you’re at that system level, whatever it is you’re building becomes a key part of it as well.

Thinking about the whole system design, a lot of individual aspects of it, that’s great. Are there key design considerations and or potential trade-offs when implementing die-to-die interfaces between these off-disk shelf chiplets that use different process nodes?

For me, think you’ve got to certainly be careful about the heating in particular. I’m not aware of one yet, but I think that we have to have something similar to what we’ve done with the Liberty files in place and route, where you can define under what conditions that block is going to work within your chip.

Now we have to say, under what temperature conditions is this chip going to still be within whatever range that you want when it’s placed inside of the package so that you’re not going to have thermal runaway problems or create stresses that you didn’t expect and have reliability issues as a result and warped edges and other issues.

One thing here is basically being able to back annotate the temperature information and potentially the stress information to the chip netlist. So while you do simulation, you can make sure it’s within spec. So the need for this will start to emerge. I don’t believe this is the case now, but in the future I can see this happening as part of the sign-off process.

Well, it’s been a great discussion. Any final thoughts before we wrap this up?

To me, it’s an exciting area. A lot of innovation, a lot of quickly moving and changing parts. My background is in physics, so it’s bringing me back home to some of the stuff that I learned years ago and how those come together and interact. I’m just really excited about it in general. I think there’s a lot more we’re gonna be seeing happening in the next five, 10 years.

From my perspective, I’m not a physics expert like John, but one of the things that we focus on is the system level concept. And it’s very exciting introducing that to customers from the packaging world and from the die world.

The need to do optimization and taking all effects into account and having one single cockpit solution to iterate between different types of analysis is very exciting.

Appreciate it, guys. Thanks. To dive deeper on this topic, John has actually written a popular technical paper entitled, Preparing for the Multiphysics of Future 3D ICs. And I’ll include a link to that in the show notes for everyone to look at. Thank you, John. Tariq, thank you. Appreciate you being here. Thanks for joining me today and sharing your knowledge and insights about the necessity for early predictive multiphysics analysis in 3D IC design.

That’s it for this episode of the 3D IC podcast. To all our listeners and viewers, thanks for joining us today and be sure to check out the show notes to learn more about today’s topic. And also be sure to follow this podcast on YouTube or your favorite streaming service so you don’t miss the next episode of the 3DIC podcast. Thanks guys.