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Transistor level ESD verification in large SoC designs

Transistor level ESD verification in large SoC designs

October 31, 2016

Dina Medhat, Mentor Graphics ESD protection is critical, but difficult to verify. Using voltage propagation and logic-aware checks can help

By Design With Calibre
4 MIN READ
Automated Power Model Verification for Analog IPs

Automated Power Model Verification for Analog IPs

February 23, 2016

By Sierene Aymen and Hartmut Marquardt, Mentor Graphics Eliminating manual work during power intent verification of analog IPs reduces susceptibility…

By Design With Calibre
4 MIN READ