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CDM

Transistor level ESD verification in large SoC designs

Transistor level ESD verification in large SoC designs

October 31, 2016

Dina Medhat, Mentor Graphics ESD protection is critical, but difficult to verify. Using voltage propagation and logic-aware checks can help

By Design With Calibre
4 MIN READ
The Changing (and Challenging) IC Reliability Landscape

The Changing (and Challenging) IC Reliability Landscape

September 8, 2015

By Matthew Hogan, Mentor Graphics Reliability issues have gone way beyond DRC and LVS verification…

By Design With Calibre
6 MIN READ