Part 7: The 2020 Wilson Research Group Functional Verification Study

IC/ASIC Design Trends This blog is a continuation of a series of blogs related to the 2020 Wilson Research Group…

Part 6: The 2020 Wilson Research Group Functional Verification Study

FPGA Language and Library Trends This blog is a continuation of a series of blogs related to the 2020 Wilson…

Part 5: The 2020 Wilson Research Group Functional Verification Study

This blog is a continuation of a series of blogs related to the 2020 Wilson Research Group Functional Verification Study. …

Portable Stimulus 2.0 Ready for Public Review

As vice-chair of the Accellera Portable Stimulus Working Group, it is my pleasure to announce that the Portable Test and…

Part 2: The 2020 Wilson Research Group Functional Verification Study

In my previous blog, I introduced the 2020 Wilson Research Group Functional Verification Study (click here). The objective of my previous…

Part 1: The 2020 Wilson Research Group Functional Verification Study

In my previous blog, I introduced the 2020 Wilson Research Group Functional Verification Study (click here). The objective of my previous…

Understanding and Minimizing Study Bias (2020 Study)

This blog is a continuation on the 2020 Wilson Research Group Functional Verification Study blog series. A big concern when…

Prologue: The 2020 Wilson Research Group Functional Verification Study

This is the first in a sequence of blogs that presents the findings from our new 2020 Wilson Research Group…

SystemVerilog Race Condition Challenge Responses

SystemVerilog Race Condition Challenge Responses

As promised, here is my response to Siemens EDA’s SystemVerilog Race Condition Challenge. Race #1 Blocking and non-blocking assignments  …