DVCon USA 2022 How to Avoid the Pitfalls of Mixing Formal and Simulation Coverage

Preview of DVCon 2022 — How to Avoid the Pitfalls of Mixing Formal and Simulation Coverage

With eight papers in two separate sessions focused exclusively on formal verification, one could assert (pun intended) that this year’s…

Why Is My Coverage The Way It Is?

Coverage is as Coverage does Writing coverage is an art. At least it is a skill which takes imagination, practice…

Part 9: The 2020 Wilson Research Group Functional Verification Study

IC/ASIC Verification Technology Adoption Trends This blog is a continuation of a series of blogs related to the 2020 Wilson…

Part 5: The 2020 Wilson Research Group Functional Verification Study

This blog is a continuation of a series of blogs related to the 2020 Wilson Research Group Functional Verification Study. …

A Little Verilog Knowledge Goes A Long Way in Understanding How SystemVerilog Constraints Work

A Little Verilog Knowledge Goes A Long Way in Understanding How SystemVerilog Constraints Work

In its simplest form, a constraint is nothing more than a Boolean expression with random variables where the solver is…

How to Reduce the Complexity of Formal Analysis – Part 2 – Reducing the Complexity of Your Assumptions

How to Reduce the Complexity of Formal Analysis – Part 2 – Reducing the Complexity of Your Assumptions

When using formal property checking, users often encounter “inconclusive” results; meaning the combined complexity of the design, assertions, and assumptions…

Part 5: The 2014 Wilson Research Group Functional Verification Study

Part 5: The 2014 Wilson Research Group Functional Verification Study

FPGA Verification Technology Adoption Trends This blog is a continuation of a series of blogs related to the 2014 Wilson…