Part 7: The 2012 Wilson Research Group Functional Verification Study

Part 7: The 2012 Wilson Research Group Functional Verification Study

Testbench Characteristics and Simulation Strategies This blog is a continuation of a series of blogs that present the highlights from…

A Short Class on SystemVerilog Classes

A Short Class on SystemVerilog Classes

It is often said that the English language is one of the most difficult languages to learn: inconsistent spelling rules;…

IEEE Approves Revised SystemVerilog Standard

IEEE Approves Revised SystemVerilog Standard

IEEE Std. 1800™-2012 Officially Ratified The IEEE Standards Association (SA) Standards Board (SASB) officially approved the latest SystemVerilog revision, Draft…

OVM Gets Connected

OVM Gets Connected

OVM Bridges SystemVerilog and SystemC Languages When UVM Connect was first released, the multilingual connection between IEEE Std. 1800™ (SystemVerilog)…

How Did I Get Here?

How Did I Get Here?

Remembering Don Loughry “How did you get involved in standards,” I was asked. On a business trip to India in…

TLM Becomes an IEEE Standard

TLM Becomes an IEEE Standard

IEEE Announces Revision to IEEE 1666™ – Adds Transaction-Level Modeling Support A significant step forward to address standards for advanced…

Verification Issues Take Center Stage

Verification Issues Take Center Stage

Is Legacy Holding You Back? Harry Foster, Mentor’s Verification Chief Scientist, will take center stage to give live presentations on…

Accellera & OSCI Unite

Accellera & OSCI Unite

System Standards Worlds Initiate Unification Accellera, who brought us SystemVerilog, and the Open SystemC Imitative (OSCI), who brought us SystemC…

The IEEE’s Most Popular EDA Standards

The IEEE’s Most Popular EDA Standards

How do your favorites rank? Have you ever wondered how popular the different IEEE standards for electronic design automation are?…