OVM Gets Connected

OVM Gets Connected

OVM Bridges SystemVerilog and SystemC Languages When UVM Connect was first released, the multilingual connection between IEEE Std. 1800™ (SystemVerilog)…

How Did I Get Here?

How Did I Get Here?

Remembering Don Loughry “How did you get involved in standards,” I was asked. On a business trip to India in…

TLM Becomes an IEEE Standard

TLM Becomes an IEEE Standard

IEEE Announces Revision to IEEE 1666™ – Adds Transaction-Level Modeling Support A significant step forward to address standards for advanced…

Verification Issues Take Center Stage

Verification Issues Take Center Stage

Is Legacy Holding You Back? Harry Foster, Mentor’s Verification Chief Scientist, will take center stage to give live presentations on…

Accellera & OSCI Unite

Accellera & OSCI Unite

System Standards Worlds Initiate Unification Accellera, who brought us SystemVerilog, and the Open SystemC Imitative (OSCI), who brought us SystemC…

The IEEE’s Most Popular EDA Standards

The IEEE’s Most Popular EDA Standards

How do your favorites rank? Have you ever wondered how popular the different IEEE standards for electronic design automation are?…

Part 8: The 2010 Wilson Research Group Functional Verification Study

Part 8: The 2010 Wilson Research Group Functional Verification Study

Language and Library Trends This blog is a continuation of a series of blogs, which present the highlights from the…

IEEE Standards in India

IEEE Standards in India

IEEE Standards Association Hosts Design Automation Standardization Workshops in Bangalore & Delhi I, along with several other individuals, will participate…