PCI Express 8.0: Powering AI, Cloud, and HPC with Transformative Interconnect Technology

PCIE Gen 8 is available now!

PCIe Express 8.0 is a fundamental leap forward in interconnect technology. By doubling data rates to an unprecedented 256 GT/s per lane, PCIe Gen8 promises to unlock new possibilities across industries, from enabling more sophisticated AI training workflows to supporting the complex AI models and multi-sensor ecosystems that will define next-generation vehicles.

DVCon US 2026 Keynote Verification Convergence

DVCon US Keynote: Why Verification Must Evolve in the Convergence Era

At DVCon US 2026, a keynote delivered by three speakers—Abhi Kolpekwar (Siemens EDA), Jean-Marie Brunet (Siemens EDA), and Alon Shtepel…

DVCon U.S. 2026 to be held at March 2-5, 2026

Siemens at DVCon U.S. 2026

DVCon U.S. returns to a larger venue at the Hyatt Regency Santa Clara. The expanded rooms and exhibit hall are intended to support a program heavily focused on AI in verification.

FutureCast 2026

FutureCast 2026: A Special Holiday Edition of BUGGED OUT

As another year closes, the semiconductor industry finds itself in a moment of transition—one where the pace of innovation is…

BUGGED OUT PODCAST

Introducing BUGGED OUT — A new bite-sized podcast for verification engineers

BUGGED OUT Podcast

New RTL Modeling Constructs in Verilog

I’ve been packing up my office as Siemens is closing my location. This marks the longest I’ve ever spent in a single office, a whopping 15 years. Coincidentally, I was in the same building earlier with another company, Avant! for an additional 2 years. I’ve got a box of stuff from previous jobs that I rarely unpack. But it happened to go through it and found the proceedings from what was to become the first DVCon in 1992. I doubt these proceedings exist anywhere in digital form.

In the proceedings was a paper I published about a new RTL modeling construct I added to Verilog before it became an IEEE standard. It eventually became known as a NonBlocking Assignment (NBA).

From manageability to 3.0: Unlocking the future with UCIe verification

The semiconductor industry is steadily moving toward multi-die integration, where chiplets from different sources are combined within a single package (known as a system in package or SiP) to deliver higher performance, scalability, and efficiency. The Universal Chiplet Interconnect Express (UCIe) standard is the backbone of this movement, offering a high-bandwidth, low-latency interconnect that enables heterogeneous chiplets to operate as one system.

UCIe 3.0 raises the bar once again. By adding higher data rates, runtime recalibration, priority sideband messaging, low-power sideband operation, and circular buffer transport, the standard improves both performance and efficiency. But it also increases verification complexity.

Pushing boundaries: Smarter verification for UCIe multi-die systems

The semiconductor industry is at a turning point. As demand for higher performance and energy efficiency continues to grow, chipmakers…

No Reset? No Worries! Smarter Ways to Tackle RDCs to NRRs

As system-on-chip (SoC) designs continue to evolve, they’re not just expanding in size—they’re growing in complexity. Among the many challenges…