Industry: Electronic Design Automation

Filter by:

Portable Stimulus and VIP: Like a Hand in a Glove

August 8, 2024

One of my favorite things about DAC is the ability to share with so many of you some details of…

By Tom Fitzpatrick
2 MIN READ
Circuit board with chip and binary data depicting interface Protocol Verification

Announcing Avery UCIe 2.0 Verification IP from Siemens EDA

August 6, 2024

Announcement: Siemens EDA are excited to announce availability of our Verification IP products for UCIe version 2.0, coincident with today’s…

By Gordon Allan
3 MIN READ

Join us at Accellera’s DAC Luncheon to discuss PSS

June 7, 2024

Portable Test & Stimulus Standard Takes Center Stage at Accellera’s DAC Luncheon.  The luncheon will be held on Tuesday, June…

By Dennis Brophy
2 MIN READ

Navigating Reset Domain Crossings to Safety in Complex SoCs

May 21, 2024

As the complexity of system-on-chip (SoC) designs escalates, driven by the demand for more integrated functionalities and higher performance, electronic…

By Reetika
3 MIN READ
Simulation is Key in design verification process

The importance of simulation in the pursuit of absolute speed!

April 2, 2024

A casual conversation with an ex-insider of the high frequency trading sector reveals surprising details about simulation and their design-verification process

By Sunil Sahoo
3 MIN READ

UVM Objections at DVCON US 2024 – and Grape Jelly

February 22, 2024

Boiling Grape Jelly Stay with me – trust me. There’s a tie in to UVM Objections and DVCON US 2024….

By Rich Edelman
3 MIN READ

Accellera Day at DVCon U.S. 2024

February 19, 2024

DVCon U.S. 2024 will be a week packed with paper sessions, tutorials, panels, keynotes and more on the latest in…

By Dennis Brophy
2 MIN READ

IEEE Honors Siemens Employees for Dedication to Standards Development

December 12, 2023

Annually, the IEEE Standards Association (IEEE SA) recognizes outstanding participation across a variety of technical areas of standards development, leadership,…

By Tom Fitzpatrick
2 MIN READ

Decoding LLM Hallucinations: Insights and Taming them for EDA Applications

June 15, 2023

What are Large Language Model’s hallucinations. LLMs will be powerful EDA productivity tool once we know what caused it and how to deal with their adverse effects.

By Dan Yu
6 MIN READ