VIP: Accelerating SoC Design Verification Your SoC designs have grown more complex, not just by the sheer number of transistors…
Although we had a very successful Portable Stimulus tutorial at DVCon US, there were still a couple of points of…
Just getting around to gathering my thoughts about the great week we had at DVCon U.S. As Program Chair for the…
My last blog post was written a few years ago before attending a conference when I was reminiscing about the…
We recently reached yet another important milestone in the life of the Universal Verification Methodology. The IEEE 1800.2 UVM Standard…
Over the past decade or so, the state of the art in design verification has taken a huge leap forward…
Face facts: power supply nets are now effectively functional nets, but they are typically not defined in the design’s RTL….
Happy Holidays! Hopefully, wherever you are you are enjoying some time off. At our house, we’re planning a large dinner,…
Deeper Dive into First Silicon Success and Safety Critical Designs This blog is a continuation of a series of blogs…
