Verilog & VHDL Debug & Weeding

A short exploration through using better debugging tools for better productivity.

Siemens EDA at the 59th Design Automation Conference

Mark your calendars for the upcoming 59th Design Automation Conference, and welcome back to the beautiful city by the bay—San…

Engineering Tools

Clearing the Fog of ISO 26262 Tool Qualification

Introduction Developing products to the ISO 26262 standard requires many activities across multiple disciplines. One of those activities is ensuring…

RISC-V

Do You Know for Sure Your RISC-V RTL Doesn’t Contain Any Surprises?

Given the relative novelty and complexity of RISC-V RTL designs, whether you are buying a commercially supported core or downloading…

ADAS_Empty_Cockpit

Navigating the Intersection of Safety and Security

Automotive IC safety and security continue to be hot topics across the industry, and one phrase you may often hear…

Growing Complexity of Automotive ASICs

I was recently asked to compile some data from our 2020 Wilson Research Group Functional Verification Study focused specifically on…

Meet Siemens at GOMACTech

See you at GOMACTech

Going to GOMACTech Siemens is going to GOMACTech, and I’ll be going as well as the Aerospace and Defense Solutions…

Verification Horizons - March 2022 Issue

Verification Horizons DVConUS 2022 Issue is Out!

The DVConUS 2022 issue of our Verification Horizons newsletter is now available. As always, we have a great slate of…

DVCon USA 2022 How to Avoid the Pitfalls of Mixing Formal and Simulation Coverage

Preview of DVCon 2022 — How to Avoid the Pitfalls of Mixing Formal and Simulation Coverage

With eight papers in two separate sessions focused exclusively on formal verification, one could assert (pun intended) that this year’s…