To UVM Config or Not at DVCON US – Can chatGPT do it better?

It’s all about speed and productivity for Verification Engineers and Designers. And of course, the UVM is the ticket, and…

osmosis 2022 - December 8, 2022 in Munich

Osmosis – our annual event for formal verification users – is back F2F this December 8, 2022!

Attention anyone interested in Formal Verification: after a hiatus due to you-know-what, osmosis is back in-person this coming December 8…

DAC Skytalk: Joe Sawicki on “Delivering ‘Smarter’ Faster – The Future of EDA & AI”

It’s hard to believe that the Design Automation Conference (DAC) is coming up in less than two weeks. As always,…

How to Mitigate the Impact of Security and Safety Flaws on Automotive ICs

Nearly 7 years ago security researchers uncovered how to remotely access and control the steering, cruise control, and braking system…

Siemens EDA at the 58th Design Automation Conference

Welcome to the 58th Design Automation Conference, and welcome back to the beautiful city by the bay—San Francisco! The 58th…

First day of school 2021 - 2022

Learn Formal the Easy Way

The sight of kids going back to school can prompt feelings of joy and renewal – or trigger less pleasant…

GSA Leadership Summit: New Paradigms – New Opportunities

Edge devices are generating data that needs to be analyzed in real time using machine learning or used to train models in the cloud. This GSA 2021 Silicon Leadership Summit session deep dives into innovations in the intelligent edge and the complexity of ensuring security.

SystemVerilog

The Semantics of SystemVerilog Syntax

Trying to grasp any programming language from scratch can be a difficult task, especially when you start by reading the…

SystemVerilog

P1800-2023 Kick-Off Meeting

There will be an informational kick-off meeting of the P1800 Working group for the next revision of the standard on Thursday, December 17th