OVM/UVM at DAC 2010
Visit Booth 1350 – The hub of OVM/UVM Activity at DAC
The OVM World booth at the Design Automation Conference (#1350) will feature user and partner presentations on OVM/UVM, a live discussion by prominent verification experts and a Tuesday cocktail reception from
4:30 p.m. to 6:00 p.m.
The Open Verification Methodology (OVM) is the industry’s open and interoperable solution, guaranteed to run on multiple simulators, supporting multiple design languages, and is the basis for the Accellera UVM standard. The OVM enables scalability and reuse, fostering a vibrant verification ecosystem. OVMworld.org is the one-stop site for the OVM open-source library, documentation, and community contributions.
Featured half-hour presentations at the booth will include those listed below. In addition to the presenting company and presentation title, full presentation abstracts can be found at http://www.ovmworld.org/tradeshows.php.
Monday (June 14th)
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10 a.m. |
Silicon Interfaces OVM-based Verification Methodology VIP permits Silicon Interfaces to release Gigabit Ethernet MAC to industry with zero defect guarantee |
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11 a.m. |
Accellera VIP Technical Subcommittee Update |
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1 p.m. |
Verilab Simulation-Based FlexRay™ Conformance Testing – an OVM success story |
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2 p.m. |
AMIQ OVM Support in DVT |
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3 p.m. |
Mentor Graphics & Cadence OVM and UVM Update |
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4 p.m. |
Nsys SuperSpeed your USB 3.0 Verification with OVM based nSys Verification IP |
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5 p.m. |
Duolog OVM/UVM from a single spec |
Tuesday (June 15th)
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9 a.m. |
Aldec OVM/UVM for FPGAs: The End of Burn and Churn? |
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10 a.m. |
Sunburst Design Virtual Interface Techniques for OVM |
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1 p.m. |
Xilinx Beyond a common base class library: reduce work by reusing OVM agents on common interfaces |
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2 p.m. |
Doulos The Communication and Customization Mechanisms in OVM and UVM |
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3 p.m. |
Mentor Graphics & Cadence OVM and UVM Update |
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4 p.m. |
Methodology Experts Discussion | |
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5 p.m. |
Cocktail Networking Event |
Wednesday (June 16th)
| 9 a.m. | Denali Denali’s PureSpec: OVM-compatible VIP for bus and I/O protocols |
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| 10 a.m. | Sibridge Successful OVM deployment |
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| 11 a.m. | Agnisys Agile methods for OVM |
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| 2 p.m. | TSMC ESL to RTL Verification – Progressive Refinement and Reuse Paradigm. TSMC Open Innovation Platform. |
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| 3 p.m. | Mentor Graphics & Cadence OVM and UVM Update |
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| 4 p.m. | Agnisys Automatic Generation of OVM Registers |
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| 5 p.m. | Duolog GNAT |
