IEEE-SA EDA & IP Interoperability Symposium
Design and verification flows are multifaceted and predominantly built by bringing tools and technology together from multiple sources. The tools from these sources build upon IEEE standards – several IEEE standards. What started with VHDL (IEEE 1076™) and Verilog/SystemVerilog (IEEE 1800™) and their documented interfaces has grown. As more IEEE standards emerged and tools and technology combined these standards in innovative and differentiated ways the industry would benefit from an ongoing open and public discussion on interoperability. The IEEE Standards Association (IEEE-SA) continues with this tradition started by my friends at Synopsys with the IEEE-SA EDA & IP Interoperability Symposium. And for 2015, I’m pleased to chair the event.
Anyone working on or using design and verification flows that depend on tool interoperability as well as design and verification intellectual property (IP) working together will benefit from attending this symposium. The symposium will be held Wednesday, 14 October 2015, at the offices of Cadence Design Systems in San Jose, CA USA. You can find more information about the event at the links below:
A keynote presentation by Dan Armbrust, CEO Silicon Catalyst, opens the event with a talk on Realizing the next growth wave for semiconductors – A new approach to enable innovative startups. If you are one of the Silicon Valley innovators, you might like to hear what Dan shares on this next growth wave. From my perspective, I suspect it will include being more energy conscious in how we design. The work on current and emerging IEEE standards that address those energy concerns will follow. We will review what the conclusions were from the DAC Low Power Workshop and leadership from the IEEE low power standards groups will discuss what they are doing in context of Low Power Workshop.
We then take a lunch break and celebrate 10 Years of SystemVerilog. The first IEEE SystemVerilog standard (IEEE Std. 1800™-2005) was published in November 2005. It seems fitting we celebrate this accomplishment. Joining many of the participants in the IEEE SystemVerilog standardization effort for this celebration will be participants from the Accellera group that incubated it before it became an IEEE standard. We won’t stop with just celebrating SystemVerilog. We will also share information on standards projects that have leveraged SystemVerilog, like UVM, which has recently become a full fledged IEEE standards project (IEEE P1800.2). With so many people who have worked on completed and successful IEEE standards, Accellera offered to bring its Portable Stimulus Working Group members over for a lunch break during their 3-day face-to-face Silicon Valley meeting to mingle with them, to learn from them and hopefully be inspired by them as well. Maybe some of the success of building industry relevant standards can be shared between the SystemVerilog participants and Accellera’s newer teams.
We will then return to a focus on energy related issues with our first topic area being on power modeling for IP. Chris Rowen, Cadence Fellow, will take us through some recent experiences on issues his teams have faced driving even higher levels of power efficiency from design using ever more design IP. Tails from the trenches never get old and offer us insight on what we might do in the development of better standards to help address those issues. While Chris will point to a lot of issues when it comes to the use of design IP, I believe these issues are only compounded when it comes to the Internet of Things (IoT). We have assembled a great afternoon panel to discuss if the “ultimate power challenge” is IoT. I can’t wait to hear what they say.
Lastly, when we pull all these systems together, LSI package board issues pose a design interoperability challenge as well. The IEEE Computer Society’s (CS) Design Automation Standards Committee (DASC) has completed another standard developed primarily outside of North America. The DASC has a long history of global participation and significant standards development outside of North America, like is the case for VHDL AMS (IEEE 1076.1). We will hear from the IEEE 2401™-2015 leadership on their newly minted IEEE standard and the LSI package board issues that have been addressed.
We don’t have time to highlight all the EDA & IP standards work in the IEEE, but our principle theme to address issues of power in modern design and verification led us to focus on a subset of them. So, if your favorite standard or topic area does not appear in the program, let me know and we can add that to our list to consider next year. And when I say “we,” the work to put together an event like this takes a lot of people. All of us are interested in what we should do for next year and what your input is to us. For me, in addition to working to collect this, I also need to thank those who did all the work to make this happen. I’ve often said, as chair, you let the others do all the work. It has been great to collaborate with my IEEE-SA friends, my peers at the other two Big-3 EDA companies. It has also been great to get the input and advice on the Steering Committee from two of the world’s largest silicon suppliers (Intel & TSMC) and to include for the first time, support from standards incubators Accellera Systems Initiative and Si2.
