Part 10: The 2014 Wilson Research Group Functional Verification Study
ASIC/IC Language and Library Adoption Trends
This blog is a continuation of a series of blogs related to the 2014 Wilson Research Group Functional Verification Study (click here). In my previous blog (click here), I presented our study findings on various verification technology adoption trends. In this blog, I focus on language and library adoption trends.
As previously noted, the reason some of the results sum to more than 100 percent is that some projects are using multiple languages; thus, individual projects can have multiple answers.
Figure 1 shows the adoption trends for languages used to create RTL designs. Essentially, the adoption rates for all languages used to create RTL designs is projected to be either declining or flat over the next year, with the exception of SystemVerilog.
Figure 1. ASIC/IC Languages Used for RTL Design
Figure 2 shows the adoption trends for languages used to create ASIC/IC testbenches. Essentially, the adoption rates for all languages used to create testbenches are either declining or flat, with the exception of SystemVerilog. Nonetheless, the data suggest that SystemVerilog adoption is starting to saturate or level off at about 75 percent.
Figure 2. ASIC/IC Languages Used for Verification (Testbenches)
Figure 3 shows the adoption trends for various ASIC/IC testbench methodologies built using class libraries.
Figure 3. ASIC/IC Methodologies and Testbench Base-Class Libraries
Here we see a decline in adoption of all methodologies and class libraries with the exception of Accellera’s UVM3, whose adoption increased by 56 percent between 2012 and 2014. Furthermore, our study revealed that UVM is projected to grow an additional 13 percent within the next year.
Figure 4 shows the ASIC/IC industry adoption trends for various assertion languages, and again, SystemVerilog Assertions seems to have saturated or leveled off.
Figure 4. ASIC/IC Assertion Language Adoption
In my next blog (click here) I plan to present the ASIC/IC design and verification power trends.
Quick links to the 2014 Wilson Research Group Study results
- Prologue: The 2014 Wilson Research Group Functional Verification Study
- Understanding and Minimizing Study Bias
- Part 1 – FPGA Design Trends
- Part 2 – FPGA Verification Effort Trends
- Part 3 – FPGA Verification Effort Trends (Continued)
- Part 4 – FPGA Verification Effectiveness Trends
- Part 5 – FPGA Verification Technology Adoption Trends
- Part 6 – FPGA Verification Language and Library Adoption Trends
- Part 7 – ASIC/IC Design Trends
- Part 8 – ASIC/IC Resource Trends
- Part 9 – ASIC/IC Verification Technology Adoption Trends
- Part 10 – ASIC/IC Language and Library Adoption Trends
- Part 11 – ASIC/IC Power Management Trends
- Part 12 – ASIC/IC Verification Results Trends
- Conclusion: The 2014 Wilson Research Group Functional Verification Study
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Hi Harry,
Do you have data on what Verification methodology is used in regards to the design size.
It would be interesting to see what design size the UVM adoption drops off at.
I would venture to guess the smaller designs haven’t adopted UVM yet.
Any thoughts?
Hi Eric,
Actually, I have done deeper analysis on this and I found that for projects working on designs less than 5M gates, there was 64% industry adoption of UVM. For projects working on designs between 5M-80M gates, there is 82% industry adoption. And for projects working on designs greater than 80M gates, there is 74% industry adoption. The data suggest that UVM is now mainstream.