Electronics & Semiconductors - Tessent Solutions

How to master DFT for tile-based designs

October 23, 2022

Hierarchical designs that are tile-based or abutment based physical blocks are predominant in today’s chips. Having no logic present at the chip-level calls for new approaches to testing these tile-based architectures. How a design for test (DFT) architecture can support tile-based designs is the focus of this presentation from U2U 2022.

By Tessent Solutions

2 MIN READ

A new way of measuring heterogeneous SoC performance

Explore a new way to measure heterogenous SoC performance at the Linley Fall Processor Conference

October 22, 2022

Join Siemens at the Linley Fall Processor Conference, the two-day event focusing on processors and IP cores used in embedded, communications, automotive, IoT,
and server designs.

By Tessent Solutions

2 MIN READ

Tessent at ISTFA 2022

October 21, 2022

Join Tessent at the 48th International Symposium for Testing and Failure Analysis, the premier event for the microelectronics failure analysis community.

By Tessent Solutions

< 1 MIN READ

Efficient and effective DFT for 3D stacked die

August 22, 2022

Yes, there is a path to a scalable, affordable, and comprehensive DFT solution for 3D ICs.

By Martin Keim

6 MIN READ

Chip data joins the party with Tessent Host Services software

June 23, 2022

Siemens’ Tessent Embedded Analytics IP and software, Host Services software opens the lines of communication with your chip and brings SLS one step closer to reality.

By Tessent Solutions

2 MIN READ