By Ron Press, Mentor Graphics Why hasn’t IC test become a bottleneck in creating ever more advanced semiconductors? In this…
By Ron Press, Mentor Graphics Complete all the DFT work weeks earlier than usual by using a hierarchical test…
As IC makers move to smaller geometries and complex FinFETs, the existing fault models and test patterns are becoming less…
To control test cost, the order in which test patterns are created and applied matters…
Tessent is a finalist in the influential Elektra Awards. We love awards and think you should too.
By Stephen Pateras, Mentor Graphics Two DFT-related rules for success are as true today as they were 30 years ago
By Rick Fisette, Mentor Graphics Remove ATPG from the critical path to tapeout with hierarchical DFT plus test pattern retargeting…
By Geir Eide, Mentor Graphics What to know about today’s scan diagnosis and yield analysis technologies…
By Geir Eide and Jonathan Muirhead Analyzing fail data with pattern matching helps companies identify yield limiters faster to increase…
