Memory BIST for automotive designs

Memory BIST for automotive designs

By Steve Pateras, Mentor Graphics Memory BIST is evolving to meet the demands of automotive ICs.  

Addressing Moore’s Law with the First Law of Real Estate: Location, location, location

Addressing Moore’s Law with the First Law of Real Estate: Location, location, location

By Beth Martin with Steve Pateras, Mentor Graphics Mentor’s novel EDT test point technology dramatically reduces ATPG pattern volume

Cell-aware test can be “Awarding”

Cell-aware test can be “Awarding”

By Ron Press, Mentor Graphics Inventing Cell-aware ATPG earned Mentor’s Friedrich Hapke the 2015 Bob Madge Innovation Award.

A flexible flow for inserting embedded compression logic in RTL

A flexible flow for inserting embedded compression logic in RTL

By Ron Press, Mentor Graphics Inserting test compression logic just got a lot easier.

New test points slash ATPG test pattern count

New test points slash ATPG test pattern count

By Ron Press, Mentor Graphics Want to see a big reduction in pattern count compared to the best ATPG compression?

Test Points are Trending

Test Points are Trending

By Ron Press, Mentor Graphics Mentor’s EDT test points slash pattern count, test time and cost. But how about at-speed…

Manage Giga-Gate Testing Hierarchically

Manage Giga-Gate Testing Hierarchically

By Ron Press, Mentor Graphics Reuse block test patterns at the top level to control test time and cost with…

Test memories at-speed with a slow clock

Test memories at-speed with a slow clock

By Martin Keim, Mentor Graphics Most memory tests don’t depend on the high-speed clock

Using EDT Test Points to reduce test time and cost

Using EDT Test Points to reduce test time and cost

By Vidya Neerkundar, Mentor Graphics New EDT Test Points are the next big thing in ATPG test compression