The new reference flow jointly developed by Arm and Mentor for hierarchical DFT and ATPG with Tessent is described in…
This video, the last in a series of three, discusses the Tessent platform capabilities and the reference flows, test cases,…
Excerpt from article: “Determining Where Power Analysis Matters Most” Getting more granular with power Krishnaswamy noted that RTL power vs. gate…
DFT designers often use boundary scan chains for 1149.1 or 1149.6 interconnect tests. This video provides tips on how to…
Excerpt from article: “Mentor Highlights HLS Customer Use in Automotive Applications” This is where HLS shines. You can develop code…
Excerpt from article: “Hardware-Software Co-Design Reappears” It was hoped that co-design would bring hardware and software teams closer together. “It…
Learn about the DFT logic that can be used to disable and enable sets/resets.
Excerpt from article: “Power Is Limiting Machine Learning Deployments” The total amount of power consumed for machine learning tasks is…
Excerpt from article: “Konica Minolta Talks About High-Level Synthesis using C++“ In the early days of chip design circa 1970’s…
