Cut in-system time for automotive ICs

Cut in-system time for automotive ICs

A new logic built-in-self-test (LBIST) technology significantly improves cycle time for in-system tests of automotive devices.

SemiEngineering: Improving Algorithms With High-Level Synthesis

SemiEngineering: Improving Algorithms With High-Level Synthesis

Excerpt from article: “Improving Algorithms With High-Level Synthesis” Most computer algorithms today are developed in high-level languages on general-purpose computers….

Re-use high-speed IOs/SERDES for scan test with IEEE 1149.10

Re-use high-speed IOs/SERDES for scan test with IEEE 1149.10

Learn about how Mentor and our partners, Advantest and Teradyne, are getting behind the IEEE 1149.10 standard for re-use of…

Test technologies enabling AI

Test technologies enabling AI

At the Silicon Valley DFT and Test Conference in Santa Clara, CA on October 23, the tight-knit community of DFT…

50 Years of International Test Conference

50 Years of International Test Conference

In 1970, the Beatles officially split, Apollo 13 narrowly averted disaster, paisley and stripes somehow went together, and the International…

Video tutorial: How to Increase Volume Scan Diagnosis Throughput by 10X

Video tutorial: How to Increase Volume Scan Diagnosis Throughput by 10X

Performing volume scan diagnosis on today’s large, advanced node designs puts outsized demands on turn-around-time and compute resources. Mentor offers…

Master the design and verification of next gen transport: Part Two – high-level synthesis

Master the design and verification of next gen transport: Part Two – high-level synthesis

Excerpt from article: “Master the design and verification of next gen transport: Part Two – high-level synthesis” Part one of…

AI Hardware Summit, Report #2: Lowering Power at the Edge with HLS

AI Hardware Summit, Report #2: Lowering Power at the Edge with HLS

Excerpt from article: “AI Hardware Summit, Report#2: Lowering Power at the Edge with HLS” I previously wrote a blog about a…

Master the design and verification of next gen transport: Part One – overview

Master the design and verification of next gen transport: Part One – overview

Excerpt from article: “Master the design and verification of next gen transport: Part One – overview” The role of high-level…