As IC makers move to smaller geometries and complex FinFETs, the existing fault models and test patterns are becoming less effective at ensuring required levels of quality. At the same time, a growing number of ICs for automotive applications is pushing the demand for zero-defect silicon. The main problem with existing fault models is that they only consider faults on cell inputs and outputs and on interconnect lines between these cells. In other words, only faults abstracted to the netlist level are explicitly considered. Cell-aware test overcomes the limitations of traditional fault models and associated test patterns by targeting specific shorts, opens, and transistor defects internal to each standard cell, resulting in significant reductions in defective part (DPM) levels. This video introduces the Cell-aware technology, describes how to use it, and presents published silicon results.