Tessent is a finalist in the influential Elektra Awards. We love awards and think you should too.
Every industry notes their outstanding contributors, hot products, and stellar performers. The film industry has the Oscars, writers can win the Man Booker Prize, and scientists have the Nobel. The electronics industry also has awards, and although they are typically presented with less glitter and more hotel-ballroom ambiance, they are still worth noting.
One of the largest industry awards, the UK-based Elektra Awards, recognizes individual successes, technical excellence, and business successes. What is the value of awards like this? For one, it lends visibility to people and products that are changing the industry. Mentor’s customers are not using Yelp to choose us as their test solution provider, nor are they using industry award lists, but the visibility of award winners comes with validation. The products on top of the awards lists have been vetted and evaluated by industry experts. This validation builds the reputation of the product and helps to differentiate it from the competitors.
The Elektra Awards just announced the finalists in all categories. Mentor Graphics has two products that make it to the finalist round, both related to test. One is the Veloce emulator DFT App, which quickly verifies gate-level DFT circuitry before tape-out.
The other is Tessent ScanPro with EDT Test Points, which reduces pattern count over what you can get with the best available ATPG compression.
DFT tools have long used compression techniques to reduce the size of the patterns that have to be transferred to the device under test (DUT). Compression helps to manage the size of test patterns, and therefor reduce tester costs, without sacrificing test quality. While the amount of compression has improved over the years, new factors like more complex design structures and the use of additional Cell-Aware patterns are driving the need for compression levels beyond 100X. This is why Mentor Graphics created the Tessent ScanPro software with EDT (Embedded Deterministic Test) Test Points.
Test points have been around for a while and are traditionally used to improve logic BIST test coverage. They can improve either the controllability or observability of a local portion of the netlist in order to increase a circuit’s overall random pattern testability.
Tessent’s ScanPro with EDT Test Points is different. It is a unique new test point generation process that directly targets ATPG pattern volume reduction. Instead of targeting random resistant portions of a circuit, EDT Test Points are inserted into a circuit so the ATPG engine can more efficiently generate patterns. The process of selecting the test point locations is based on reducing signal assignment conflicts that arise during the pattern generation process.
The achievable pattern volume reduction depends on the number of test points used and the design characteristics, but the following published empirical results are typical of the 2X to 4X reduction in pattern count. This pattern volume reduction is in addition to the pattern reduction achieved through Tessent TestKompress® ATPG compression. We in the Tessent group know that EDT Test Points is pretty special, and we are keeping our fingers crossed that the judges for the Elektra Awards think so too.
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White Paper: EDT Test Points