To improve yield, find the design-sensitive defects

To improve yield, find the design-sensitive defects

By Matt Knowles – Mentor, A Siemens Business Whether you are trying to accelerate yield ramp on a new process…

Boost FinFET Yield with Cell-aware Scan Diagnosis

Boost FinFET Yield with Cell-aware Scan Diagnosis

By Matt Knowles – Mentor, A Siemens Business FinFETs display more defects at the transistor level, which also tend to…

Yield is Money

Yield is Money

By Matt Knowles – Mentor, A Siemens Business Have yield issues delayed your product introduction or sales? Would a 1%…

Mentor at SEMICON West

Mentor at SEMICON West

SEMICON West  fills the Moscone Center again this year with the entire electronics supply chain. You are guaranteed to learn…

My Self-driving Car Should Work Right Every Time

My Self-driving Car Should Work Right Every Time

By Stephen Pateras – Mentor, A Siemens Business I think I speak for us all when I say that strict…

Control test cost with low pin count test

Control test cost with low pin count test

By Rahul Singhal – Mentor, A Siemens Business Several design trends, including increased design sizes and the use of advanced…

The growing presence of IC Test and Yield Analysis at DAC

The growing presence of IC Test and Yield Analysis at DAC

DAC was once the playground for the core EDA topics but has broadened in a reflection of the growing connectedness…

Yasa! Mentor Focus at the European Test Symposium

Yasa! Mentor Focus at the European Test Symposium

The IEEE European Test Symposium  takes place from 22-16 May in Limassol, Cyprus. When not contemplating the stunning azure Mediterranean,…

Scan Insertion for better ATPG

Scan Insertion for better ATPG

By Vidya Neerkundar, Mentor Graphics Good scan insertion can make a difference in the quality of your automatic test pattern…