Hierarchical DFT: How to Do More, More Quickly, with Fewer Resources

By Rick Fisette, Mentor Graphics Is DFT a barrier to tapeout? Time to consider going…

Automotive Semiconductor Test

By Steve Pateras, Mentor Graphics Ensure quality and reliability in automotive ICs with the newest…

Memory BIST for automotive designs

By Steve Pateras, Mentor Graphics Memory BIST is evolving to meet the demands of automotive…

Addressing Moore’s Law with the First Law of Real Estate: Location, location, location

By Beth Martin with Steve Pateras, Mentor Graphics Mentor’s novel EDT test point technology dramatically…

Cell-aware test can be “Awarding”

By Ron Press, Mentor Graphics Inventing Cell-aware ATPG earned Mentor’s Friedrich Hapke the 2015 Bob…

A flexible flow for inserting embedded compression logic in RTL

By Ron Press, Mentor Graphics Inserting test compression logic just got a lot easier….

New test points slash ATPG test pattern count

By Ron Press, Mentor Graphics Want to see a big reduction in pattern count compared…

Test Points are Trending

By Ron Press, Mentor Graphics Mentor’s EDT test points slash pattern count, test time and…

Manage Giga-Gate Testing Hierarchically

By Ron Press, Mentor Graphics Reuse block test patterns at the top level to control…