Here’s a great opportunity to tap into the silicon bring-up knowledge of experts from Mentor and Teradyne.
The live, one-hour, online seminar “Tessent SiliconInsight ATE-Connect: Bending the bring up schedule curve in your favor” is presented by Teradyne’s Marc Hunter and Mentor’s Matthew Knowles.
When: June 16, 2020, at 5:00 PM US/Pacific. If you can’t make that date, register anyway and you’ll get the link to the recorded session afterward.
Where: Live, online with presentation and Q&A with the experts.
Cost: An hour of your precious time.
The seminar focuses on how to improve your time-to-market (TTM) for debug of a test program to production. Mentor’s ATE-Connect technology in Tessent SiliconInsight enables direct communication between Tessent DFT software and Teradyne testers, accelerating silicon bring-up from weeks to days.
Teradyne and Mentor continue to innovate with Tessent IJTAG by releasing platform support for UltraFLEX+ and enhanced capability with Tessent for embedded memory MEMBIST.
Teradyne’s PortBridge technology enables the UltraFLEX family of production testers to achieve optimized TTM by streamlining program debug, production operation, and lab correlation to test for critical IP blocks. Learn about how Teradyne’s UF+ innovations will enable future EDA innovations, which will accelerate TTM on your next silicon.
The seminar will summarize the current and upcoming challenges for bring-up of complex SoCs, show how industry partnerships spurred the development of EDA software and ATE hardware tools that work together, and demonstrate through IJTAG and MBIST case studies how to reduce bring-up from weeks to immediate results. Attendees will have chat capability and a Q&A with the experts.