Excerpt from article: “Week In Review: Design, Low Power“ Arm and Mentor are teaming up on a RTL Verification Design…
Advanced DFT is your competitive edge Every new SoC project starts with grand hopes of glory. This one will be…
The summer of 2020 featured several new webinars from the Tessent Test Solutions group at Mentor, a Siemens business. These…
Excerpt from article: “Custom Designs, Custom Problems“ You have to put margin in your architecture. You have to leave a…
Excerpt from article: “The Evolution Of High-Level Synthesis“ The first panelist was Brian Bowyer, director of engineering for Siemens EDA. Bowyer…
Excerpt from article: “Power And Performance Optimization At 7/5/3nm“ At the edge, where people are building these new AI processors,…
In a new technical paper, Ron Press, the director of technology enablement for the Tessent Test Solutions, describes the new…
The world of ATPG just changed with the introduction of a new solution that can calculate the critical-area effectiveness of…
Excerpt from article: “Panel Discussion of High Level Synthesis“ Bryan Bowyer from Siemens EDA was the first to present, and…
