Google and Tessent Streaming Scan Network at ISTFA 2024
Technology advancements have led to a significant increase in system-on-chip (SoC) complexity, necessitating the careful optimization of DFT techniques to minimize test time while ensuring high test coverage. Tessent SSN addresses today’s test challenges by revolutionizing how test data is delivered within a chip. Instead of traditional scan chains, SSN uses a packet-based network to distribute test data to multiple cores simultaneously.
A significant SSN advantage is that the bus width is determined by chip-level pin availability and not by the core size, count or EDT channel needs. This enables a standardized interface which makes SSN highly scalable regardless of changes in floor plan, core count or core content. This also significantly reduces the number of pins needed on the chip, leading to faster testing and smaller test data volumes.
In addition to addressing DFT implementation effort and test data volume, it is also important to facilitate debug, yield analysist and failure analysis (FA). SSN includes dedicated capabilities that ensure that established FA techniques such as Electrical Fault Isolation (EFA) can be used in together with SSN.
At the recent International Symposium for Testing and Failure Analysis (ISTFA 2024), Lesly Endrinal, Silicon Failure Analysis Engineering Lead at Google, presented findings on the use of Siemens Tessent Streaming Scan Network (SSN). The paper “Solving Complex Electrical Fault Isolation Challenges with Innovative DFT Strategies” introduces new features intended to facilitate failure analysis on designs tested using Tessent SSN.
The paper presents three innovative DFT features and strategies to enable electrical fault isolation in the Tessent SSN architecture, an industry first. As DFT and test technologies become more complex and inaccessible, it becomes very important for EDA vendors and designers to be more aware of the impact it has on EFI and should be more proactive in designing hooks for FA for a seamless yield bring up and design debug.
For more information, please read the ISTFA paper.
