User2User 2024: Meeting future performance demands through packaging: ChipletZ

Learn how 3DIC tech enhances compact, high-performance systems but faces verification challenges. We explore solutions and methodologies, including the use of Siemens XSI and Calibre 3DSTACK.

The evolution of machine learning (ML) in the physical design and verification of semiconductor packages

Discover how Siemens’ EDA evolution of machine learning in the physical design and verification of semiconductor packages.

User2User 2024: EMIB based advanced packaging flow – Intel Foundry

Learn how Intel uses 3DIC verification to leverage Siemens XSI & Calibre 3DSTACK for DRC, LVS, assembly checks. Explore methodologies for high-performance systems.

Why is a comprehensive workflow essential for chiplet design and today’s 3D IC architectures?

Explore this infographic to learn why a comprehensive workflow essential for chiplet design and today’s 3D IC architectures.

The multi-physics challenge: Known good die may not behave in 3D IC as stand alone!

Discover how Siemens’ EDA tackles the multi-physics challenge to achieve fast, accurate assembly-level physical verification.

Assembly Verification Flow for Silicon Interposers with Embedded Deep Trench Capacitance

User2User 2024: Assembly verification flow for silicon interposers

In this User2User 2024 session Broadcom’s Suvarna Vikhankar presents “Assembly Verification Flow for Silicon Interposers with Embedded Deep Trench Capacitance”

New innovative way to functionally verify heterogeneous 2D/3D package connectivity

New innovative way to functionally verify heterogeneous 2D/3D package connectivity

This blog introduces a white paper that addresses the challenges of verifying
package connectivity and illustrated how to use formal tools to verify connectivity for package designs.