3D IC design solutions: 2024 – Year in review

Welcome to a look back at a landmark year in 3D IC technology — 2024 was nothing short of revolutionary!…

Text that says what's new in IC Packaging 2409 next to a stylized X

What’s new in IC Packaging 2409

The 2409 release is a landmark update in the field of electronic design automation (EDA), introducing a next-generation solution for…

Siemens introduces Innovator3D IC – a comprehensive multiphysics cockpit for 3D IC design, verification and manufacturing

Innovator3D IC – a comprehensive multiphysics cockpit for 3D IC design, verification and manufacturing

Image showing physical design IP reuse with Xpedition Package designer

Embracing physical design IP reuse as a best practice

Efficiency in IC package design is becoming more important as design cycles shorten and complexity surges. One common approach to…

New innovative way to functionally verify heterogeneous 2D/3D package connectivity

New innovative way to functionally verify heterogeneous 2D/3D package connectivity

This blog introduces a white paper that addresses the challenges of verifying
package connectivity and illustrated how to use formal tools to verify connectivity for package designs.

Two people working at a white board with text onscreen that says: Multiplying engineering resources for efficient package substrate design

Multiplying engineering resources for efficient package substrate design

In the world of package substrate design, the age-old saying, “many hands make light work,” holds more truth than ever….

Image of a chip with text that says: High Bandwidth Memory integration

Managing the complexities of High Bandwidth Memory integration in high-performance computing

The utilization of High Bandwidth Memory (HBM) has become a cornerstone for high performance computing (HPC) CPUs, GPUs, and AI…

Taking 2.5D/3D IC physical verification to the next level

Taking 2.5D/3D IC physical verification to the next level

Taking 2.5D/3D IC physical verification to the next level. As package designs continue to evolve, so must the verification requirements. Designers working on even the most complex multi-die, multi-chiplet stacked configurations require enhanced checking capabilities to quickly and easily verify that the physical die are placed correctly to ensure proper connectivity and electrical behavior.

Image of a chip on a board with text that says Navigating complexities in power delivery analysis: embracing the shift-left approach

Navigating complexities in power delivery analysis: embracing the shift-left approach

The demand for increased power and performance in semiconductor packages has surged. As more die and chiplets are integrated into…