By John Ferguson and Tarek Ramadan, Mentor Graphics

Why do we need assembly design kits for IC packages?

In our last article, we talked about a project we participated in to test the feasibility of an assembly design kit (ADK) for package design verification. This time, we’d like to delve a little more into the reasons why assembly design kits are needed.

Naturally, one of the reactions to our article was “But I already have requirements from my package house. Why do I need an ADK?” True, packaging houses and outsourced semiconductor assembly and test (OSAT) companies do supply information to their customers in the form of requirements, typically as process documents or a design rule manual. Generally speaking, these requirements are relatively simple in scope, at least when compared to traditional integrated circuit (IC) process documents. While they may be very useful for designers as they start designing a component targeted for that specific fabrication, they lack a key feature: validation.

For example, almost all packaging design tools have some built-in rules, or are associated with some form of design rule checking (DRC). Each design team can interpret the document from the packaging house to create their own deck to use along the way. This is a good start, but how do you know that design team coded the rules correctly? Further, how do you know that the tool they’re using is interpreting the code as expected? Until now, there has not been a formal sign-off process.

The result? It is possible, and surprisingly quite common, for customers to send package designs to manufacturing with actual errors in them. Despite this occurrence, the result is usually not manufactured packages that don’t work. Instead, the package house spends considerable effort to review and examine every incoming design. When they find these problems, they manually fix them on their own! Not only is this a huge effort on the part of the packaging house, but it also introduces a new set of risks to the design team. How can they be sure that the introduced changes do not modify their design’s intended behavior?

So, why not just enable traditional IC physical verification? From a physical checking perspective, traditional IC verification tools rely on GDSII or similar layout formats for their inputs. Because these formats contain no information about a geometry’s placement in the vertical direction, that information is typically inferred through layer mapping. From this kind of layer mapping and the use of typical layer-naming conventions, we can infer, for example, that metal-2 is vertically higher than metal1, and lower than metal 3, and we can establish the layers’ electrical connectivity through the presence of appropriate via layers. All geometries mapped to the same layer are considered to be co-planar. Geometries on the same layer that overlap or abut are treated as if they are, in fact, a single polygon, as they will be merged during the mask generation process.

What we need for signoff-quality physical verification of packages is a completely different technique. One component of an ADK would be checks for the package layers and interacting die layers, without reference to any kind of layer mapping. Such checks would include, for example, confirmation that connections are intact within the package (die-to-die) and from the package to the outside (die-to-BGA). EDA vendors supporting the ADK would need to enhance their tools to apply these checks and enable debugging of any errors. With a design-independent, and more importantly, design-tool-independent sign-off mechanism, designers would have a way to identify and fix all known packaging issues on their own, removing all potential manufacturing risk, and eliminating the expensive and time-consuming review and correction process at the packaging house.

The other element of ADK success is ensuring that the IC tools and the package tools understand the files and data formats of each other. While this is primarily the responsibility of the EDA vendors, it will take the expertise of all three participants to ensure that integration between the two types of development kits is handled in an effective and efficient manner to enable smooth transitions between IC and package designs.

Of course, that doesn’t mean either the design company or the packaging house gets off scot-free. The packaging company must invest time and effort to create, maintain, and support the package rule decks, including the creation of regression tests to validate all the real error cases. Fortunately, this effort only needs to be done once for each manufacturing process supported, and in return, the packaging house now has a significantly lower burden of effort when reviewing incoming designs for issues. And of course, there may still be cases where a design team has design issues they cannot solve on their own. In this case, the design team may need to look to the packaging house’s expertise for assistance. This may afford the packaging house the option of creating a new pricing model to apply in these cases, versus submitted designs that are completely clean.

While the implementation of an ADK is a non-trivial effort, both design houses and OSATs receive long-term value from the investment. Design houses can develop package designs with greater confidence in the manufacturability of the design. OSATs can significantly reduce their manual verification efforts, while ensuring their resources are reserved for the most difficult and complex design issues. Yes, the initial process will require collaboration between design houses, EDA vendors, and OSATs/package houses, but the incentive to succeed is strong. Reducing the risk of design failure while simultaneously reducing the time and resources required to validate package designs is a win-win for all participants.

Authors

John Ferguson is the Director of Marketing for Calibre DRC Applications at Mentor Graphics in Wilsonville, Oregon, and has extensive experience in the area of physical design verification.

Tarek Ramadan is a Technical Marketing Engineer for Calibre Design Solutions at Mentor Graphics. He supports Calibre physical verification solutions for 2.5D-IC, 3D-IC and wafer level packaging applications.