Implicit handle: this

SystemVerilog: Implicit handles

Introduction In the last blog post [SC(SECL1] Farmer Ted asked you to keep track of his animals and you wrote some…

SystemVerilog: Class Member Visibility

SystemVerilog: Class Member Visibility

Introduction Farmer Ted wants to keep track of the animals on his property and asks you to write the code….

Connect test module with interface to design with individual ports

SystemVerilog: What is a Virtual Interface?

When I learned the SystemVerilog verification features, one concept had me baffled – virtual interfaces. What are these and why…

Parking lot with an Automobile and Pickup, plus class variables

Class Variables and $cast

Introduction My previous post showed how SystemVerilog class variables can refer to base and derived objects. This post shows you…

Base and derived classes and their handles

Class Variables and Assignments in SystemVerilog

Introduction Good OOP style says you should start your project with a common base class (or several). When you want…

Verification Class Categories

Introduction What can you describe with Object-Oriented Programming? When I learned OOP, we had cute classes like animals, cars, and…

SystemVerilog Class Variables and Objects

Introduction How can you visualize the relationship between classes and objects in SystemVerilog? This is the first post in a…

The UVM Config DB and Scope

Introduction With any large software project, you need to share information and control across widely separated blocks. In the bad…

UVM Transaction Coding Style

How to write a UVM transaction class? There has been a split in UVM – how to create a sequence…