Pool of parameterized handles in SystemVerilog

Groups of Class Specializations in SystemVerilog

Introduction In a previous post, I said that in SystemVerilog, once you specialize a class, you can not make a…

A pool of specialized classes

Dig a Pool of Specialized SystemVerilog Classes

Introduction SystemVerilog classes are a great way to encapsulate both variables and the routines that operates on them. What if…

Implicit handle: this

SystemVerilog: Implicit handles

Introduction In the last blog post [SC(SECL1] Farmer Ted asked you to keep track of his animals and you wrote some…

Connect test module with interface to design with individual ports

SystemVerilog: What is a Virtual Interface?

When I learned the SystemVerilog verification features, one concept had me baffled – virtual interfaces. What are these and why…

Parking lot with an Automobile and Pickup, plus class variables

Class Variables and $cast

Introduction My previous post showed how SystemVerilog class variables can refer to base and derived objects. This post shows you…

Base and derived classes and their handles

Class Variables and Assignments in SystemVerilog

Introduction Good OOP style says you should start your project with a common base class (or several). When you want…

Verification Class Categories

Introduction What can you describe with Object-Oriented Programming? When I learned OOP, we had cute classes like animals, cars, and…

SystemVerilog Class Variables and Objects

Introduction How can you visualize the relationship between classes and objects in SystemVerilog? This is the first post in a…

UVM Configuration DB Guidelines

UVM Configuration DB Guidelines

Introduction My previous blog posts were on static and parameterized classes to get you ready for the big game –…