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    Implicit handle: this

    SystemVerilog: Implicit handles

    September 6, 2022

    Introduction In the last blog post [SC(SECL1] Farmer Ted asked you to keep track of his animals and you wrote some…

    By Chris Spear
    4 MIN READ
    Base and derived classes and their handles

    Class Variables and Assignments in SystemVerilog

    July 12, 2021

    Introduction Good OOP style says you should start your project with a common base class (or several). When you want…

    By Chris Spear
    3 MIN READ

    Runtime checks with the $cast() method

    June 28, 2021

    Introduction Verilog was always known for its lack of type checking, treating everything as just bits strung together into vectors…

    By Chris Spear
    3 MIN READ

    Verification Class Categories

    June 21, 2021

    Introduction What can you describe with Object-Oriented Programming? When I learned OOP, we had cute classes like animals, cars, and…

    By Chris Spear
    4 MIN READ

    SystemVerilog Class Variables and Objects

    June 14, 2021

    Introduction How can you visualize the relationship between classes and objects in SystemVerilog? This is the first post in a…

    By Chris Spear
    5 MIN READ