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Siemens EDA at DVCon India 2024: Join Us for an Exciting Lineup!

September 5, 2024

We are thrilled to announce Siemens EDA’s participation in DVCon India 2024, taking place on September 18-19 at the Radisson Blu in Marathahalli, Bangalore. This year’s event promises to be a hub of innovation and knowledge-sharing, and we are excited to be a part of it.

Siemens EDA will be showcasing a range of informative sessions and exhibits designed to help you engineer a smarter future faster.

By Dennis Brophy
2 MIN READ

Accellera Day at DVCon U.S. 2024

February 19, 2024

DVCon U.S. 2024 will be a week packed with paper sessions, tutorials, panels, keynotes and more on the latest in…

By Dennis Brophy
2 MIN READ

Pro Tip: Planning to Land Your Spacecraft on Mars? You Will Need CDC, RDC, and Formal Property Checking

May 19, 2022

If you are an engineer at one of the growing number of entities looking to land a spacecraft on Mars…

By Joe Hupcey III
4 MIN READ
Cooking with a non-stick pan

Non-stick surfaces and RTL design

November 15, 2021

How to keep RTL designers from costing their co-workers dinners and bedtimes in the most efficient way possible.

By Chris Giles
2 MIN READ
What happens in Vegas…is happening in the Verification Academy and Mentor booths!

What happens in Vegas…is happening in the Verification Academy and Mentor booths!

May 16, 2019

It’s been 18 years since DAC last visited Las Vegas, and a lot has happened in verification during this period….

By Harry Foster
3 MIN READ
Significantly Improve Your FPGA Design Reliability by Using Custom CDC Synchronizers

Significantly Improve Your FPGA Design Reliability by Using Custom CDC Synchronizers

April 24, 2018

[Preface: we are presenting a paper on this topic at the upcoming SEE/MAPLD conference, May 21-24, 2018 in La Jolla,…

By Joe Hupcey III
5 MIN READ
No One Expects Gate Level CDC Verification and Glitch Detection for ASIC Signoff!

No One Expects Gate Level CDC Verification and Glitch Detection for ASIC Signoff!

February 12, 2018

[Preface: at the upcoming DVCon 2018 in San Jose, poster 4.12 addresses some of the issues raised below, as well…

By Joe Hupcey III
4 MIN READ
See You at DVCon U.S. 2018!

See You at DVCon U.S. 2018!

January 30, 2018

We hope to see you at DVCon U.S. 2018.  Mentor will showcase 17 papers and posters during the conference on…

By Dennis Brophy
5 MIN READ
Are You Struggling to Reach Timing Closure with Your Low Power Design – You May Have CDC Problems!

Are You Struggling to Reach Timing Closure with Your Low Power Design – You May Have CDC Problems!

January 7, 2016

First, if you were brought here by a desperate Google search for “timing closure tricks STA RTL” as your tape…

By Joe Hupcey III
3 MIN READ