Part 8: The 2010 Wilson Research Group Functional Verification Study

Language and Library Trends This blog is a continuation of a series of blogs, which…

The Survey Says: Verification Planning

As the saying goes: Those who fail to plan, plan to fail. With that said,…

Making formal property checking easy to use

For years one of the objectives in EDA has been to make formal property checking…

Static Verification

After spending years verifying ASICs with dynamic simulation, I started working on static verification 10…

DAC Panel: Bridging Pre-Silicon Verification and Post-Silicon Validation

I’d like to encourage you to attend the technical panel titled Bridging Pre-Silicon Verification and…

A Cliffhanger ABV Seminar, Jan 19, Santa Clara, CA

I’m excited. I’ve had the pleasure of knowing Cliff Cummings for many years, and I…

Evolution is a tinkerer

I was recently quoted in an EDA DesignLine blog as saying that “it is a…

ABV and being from Missouri…

The last industry project I worked on, before joining EDA, was an advanced chip set…