Somebody asked me a simple question: Why do need two different macros (`ovm_object_utils and `ovm_object_param_utils) to register classes with the…
IEEE Standards Association Hosts Design Automation Standardization Workshops in Bangalore & Delhi I, along with several other individuals, will participate…
Standard Co-Emulation Modeling Interface (SCE-MI) 2.1 Improves Verification Productivity The Accellera Interface Technical Subcommittee (ITC) completed version 2.1 of the…
Hi Everyone, Just wanted to let you know that the latest edition of our Verification Horizons newsletter is available here….
As the saying goes: Those who fail to plan, plan to fail. With that said, I am excited to announce…
23rd Synopsys EDA Interoperability Forum Features a Verification Session with focus on the UVM Register Package As readers of the…
United States Plays Host in Seattle, WA The IEC’s 47th General Assembly meeting opened on October 11th in Seattle, WA…
Technorati Tags: UVM,SystemVerilog,RAL,OVM The development of UVM in the Accellera VIP-TSC brings up, yet again, the age-old philosophical question: should…
UVM is Taking Shape While you have all been happily verifying your complex SoCs the Accellera VIP Technical Subcommittee (VIP-TSC),…
