Safety-Critical Design

Safety-Critical Design

Mentor Joins Arm® Functional Safety Ecosystem Mentor is pleased to join the Arm Functional Safety Partner program to bring our…

Don’t Miss the Upcoming DVClub Austin Event!

Don’t Miss the Upcoming DVClub Austin Event!

If you have a passion for design and verification, then I highly recommend that you check out the DVClub. The…

Formal Verification Done Fast

Formal Verification Done Fast

It’s not too late to register for our two-part webinar on faster formal verification. This week and next we will…

Portable Stimulus: Are you Ready for a Verification Revolution?

Portable Stimulus: Are you Ready for a Verification Revolution?

Depending on the revolution and who you happen to be within it, revolution is a risk to avoid at all…

A Little Verilog Knowledge Goes A Long Way in Understanding How SystemVerilog Constraints Work

A Little Verilog Knowledge Goes A Long Way in Understanding How SystemVerilog Constraints Work

In its simplest form, a constraint is nothing more than a Boolean expression with random variables where the solver is…

DVCon India 2019 – Let’s Meet!

DVCon India 2019 – Let’s Meet!

The design and verification of electronic systems is a global activity and Accellera has responded to make the DVCon’s more…

Portable Stimulus and the Prius Model of New Technology Adoption

Portable Stimulus and the Prius Model of New Technology Adoption

Tesla and the New Technology Adoption Curve Over the past few years, I’ve noted with interest the increasing number of…

Didn’t make it to DAC this year? We’ve got you covered!

Didn’t make it to DAC this year? We’ve got you covered!

I’ve probably mentioned in the past that DAC is one of my favorite events of the year. Aside from catching…

The Many Flavors of Equivalence Checking: Part 2, How SLEC Brings Automated, Exhaustive Formal Analysis to ECO/Bug Fix Verification

Perhaps the only Sequential Logic Equivalence Checking (SLEC) flow that is as common as the synthesis validation flow described in…