Just like time and the tides, the complexity of electronic systems, and the need to verify that they will function correctly, wait for no one. With this in mind, I invite you to attend our new “What’s New in Functional Verification” webinar series, starting on Thursday, May 14. The series will contain a total of five one-hour sessions, each containing two half-hour presentations. The series starts with a Keynote presentation (from yours truly) on “Optimizing Time to Bug,” which will describe the major trends in the industry and the challenges they pose for verification. The second presentation in this session, and all subsequent sessions will each highlight key technology and value in Mentor’s verification Platform to address these challenges. Here is an outline of the series (register for each session here):
- Session 1, May 14
- Optimizing Time to Bug: A “keynote” presentation for the series, highlighting the issues that have cropped up in recent years, including the explosion in the amount of data that must new be verified and managed and the safety and security of the data and systems they control.
- Productivity in the Questa Simulation Flow: Every step of the Questa Simulation-based verification flow has been optimized and accelerated, from regression management, to incremental compilation and elaboration, to debug and coverage.
- Session 2, May 21
- Veloce Strato: Hardware-Assisted Verification Productivity: When you consider the verification and validation challenges in new areas like AI/ML, 5G and automotive electronics, the Veloce hardware emulation platform provides the speed, visibility and ease-of-use to support you throughout the process, including silicon bring-up.
- Context-Aware Debug for Complex Heterogeneous Environments: Regardless of the verification engine, Visualizer provides both Interactive and Off-Line debug, featuring Hardware and Software Views of everything from transactions down to transistors, including software-driven verification.
- Session 3, May 28
- Maximize Your UVM Productivity with Protocol-Aware Questa Verification IP: The Questa VIP library gives you everything you need to verify standard protocols in your UVM environment. With the new Configurator GUI, it’s now even easier to take advantage of these powerful verification components to maximize the effectiveness of your UVM verification.
- Find Bugs Earlier with Strategy-Guided Stimulus: In this session, we will explore the benefits of focusing on constrained-random regression testing and coverage closure independently, through the application of strategy-guided stimulus using Questa inFact. We will also see how inFact can be used to take a structured approach to bug hunting.
- Session 4, June 4
- Improving Quality and Time-to-Market with Formal: Part 1, Automated Formal-based Apps: Questa Formal provides a powerful set of automated applications (“apps”) that can identify many challenging design issues and other hard-to-find corner cases.
- Improving Quality and Time-to-Market with Formal: Part 2, Direct Formal Property Checking: In this session we will show how formal property checking enables high-value verification long before other methods are available, exhaustively discovering any design errors that can occur
- Session 5, June 11
- CDC/RDC: This session will cover Questa’s clock- and reset-domain crossing solution will help you avoid costly design flaws like errors in clock, reset and power designs, and accelerate your time to market.
- Mentor + Siemens Provides Solutions and Expertise to Achieve Rapid Safety Compliance: The powerful combination of Mentor’s functional verification and functional safety products together with Siemens’ lifecycle management tools provide built-in guidance and automation helping you navigate the difficult waters of safety compliance.
In addition to the presentations, each session will include plenty of time for Q&A. We hope you’ll be able to join us for this informative webinar series.