Accellera announces fee-free availability of IEEE Std. 1801™-2024
Accellera announced the latest revision of the IEEE Standard for Design and Verification of Low-Power Energy-Aware Electronic Systems, also known as the Unified Power Format (UPF) 4.0, has been published by the IEEE. Fee-free access to the standard is provided courtesy of Accellera. It builds upon previous versions to provide a comprehensive framework to design and verify low-power, energy-aware electronic systems. This standard has become essential for engineers working on a wide range of power-constrained applications, from mobile devices to high-performance computing platforms. The 2024 revision introduces several significant enhancements that make it an important update for any design team focused on power optimization.
Major enhancements
One of the major enhancements in UPF 4.0 is the ability to enable interconnect between UPF supplies and arbitrary HDL types using Value Conversion Methods (VCMs) and tunneling. This allows for a more flexible and consistent representation of power intent across the design and verification flow that offers better integration between the power intent specification and the HDL implementation.
Another significant improvement is the introduction of refinable macros, which enable non-intrusive power intent updates in bottom-up verification flows. This helps streamline the verification process that allows power intent to be updated without disrupting the overall design. Refinable macros provide a way for soft IP (SIP) providers to define power intent that can be easily refined and integrated into a larger SoC design.
The standard now includes enhanced retention modeling, providing more detailed control over save/restore conditions and the effects of asynchronous set/reset signals. This allows more accurate modeling of power-managed state elements, which is crucial as state retention cell designs continue to evolve.
UPF 4.0 also supports virtual supplies and virtual equivalence that allows designers to model supplies that are not physically connected in the design. This helps improve the fidelity of power intent representation, especially for complex mixed-signal designs.
Other general updates and clarifications have been made to the standard to address emerging needs in areas like mixed-signal design, power modeling, and ease-of-use. These enhancements help make UPF 4.0 a more comprehensive and user-friendly solution to specify and verify low-power designs.
Overall impact
The updates in UPF 4.0 demonstrate a clear focus to address the growing complexity of low-power electronic design. By enhancing power state modeling, supporting flexible design flows, improving the UPF information model, and expanding retention register support, this standard equips designers with the know-how they need to tackle the power challenges of today and tomorrow. Adopting IEEE Std. 1801-2024 can help design teams stay ahead of the curve, delivering energy-efficient products that meet the ever-increasing demands of modern electronics.
Availability
The standard can be downloaded directly from the IEEE Xplore digital library via the IEEE GET Program. This easy access ensures that design teams around the work can rapidly learn and use UPF 4.0.
Source code available
Companion source code to the standard that includes SystemVerilog and VHDL examples has been extracted from the standard and can be found on IEEE SA Open at https://opensource.ieee.org/upf. In addition, practical examples that demonstrate the application of UPF in real-world scenarios have been extracted from Annex E. By embracing open-source, and fostering an active online community, the IEEE encourages designers to adopt a collaborative approach to accelerate the learning curve, identify real-world use cases, and drive continuous improvements to the standard.
Endnote of thanks
In addition to my “day job,” I am the volunteer chair of the IEEE Design Automation Standards Committee that the P1801 Low Power Working Group reports into. In this role, I want to take the opportunity to thank the P1801 Working Group and its leadership for the hard work and dedication to craft and complete this standard. There many more new things to explore in the standard and as you are addressing your low power design and verification challenges. I hope UPF 4.0 offers you the needed support to build the next generation of low power electronic systems!
